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1# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+debug,+density \2# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s3 4.align 45LBL0:6 7# Instruction format RRR8# CHECK-INST: break 1, 19# CHECK: encoding: [0x10,0x41,0x00]10break 1, 111 12# Instruction format RRRN13# CHECK-INST: break.n 114# CHECK: encoding: [0x2d,0xf1]15break.n 116 17# Instruction format RRR18# CHECK-INST: lddr32.p a319# CHECK: encoding: [0xe0,0x73,0x00]20lddr32.p a321 22# Instruction format RRR23# CHECK-INST: sddr32.p a324# CHECK: encoding: [0xf0,0x73,0x00]25sddr32.p a326 27#Instruction format RRR28#CHECK-INST: xsr a2, icount29#CHECK: encoding: [0x20,0xec,0x61]30xsr a2,icount31 32#Instruction format RRR33#CHECK-INST: xsr a2, icount34#CHECK: encoding: [0x20,0xec,0x61]35xsr.icount a236 37#Instruction format RRR38#CHECK-INST: xsr a2, icount39#CHECK: encoding: [0x20,0xec,0x61]40xsr a2, 23641 42#Instruction format RRR43#CHECK-INST: xsr a2, icountlevel44#CHECK: encoding: [0x20,0xed,0x61]45xsr a2,icountlevel46 47#Instruction format RRR48#CHECK-INST: xsr a2, icountlevel49#CHECK: encoding: [0x20,0xed,0x61]50xsr.icountlevel a251 52#Instruction format RRR53#CHECK-INST: xsr a2, icountlevel54#CHECK: encoding: [0x20,0xed,0x61]55xsr a2, 23756 57#Instruction format RRR58#CHECK-INST: xsr a2, ibreaka059#CHECK: encoding: [0x20,0x80,0x61]60xsr a2,ibreaka061 62#Instruction format RRR63#CHECK-INST: xsr a2, ibreaka064#CHECK: encoding: [0x20,0x80,0x61]65xsr.ibreaka0 a266 67#Instruction format RRR68#CHECK-INST: xsr a2, ibreaka069#CHECK: encoding: [0x20,0x80,0x61]70xsr a2, 12871 72#Instruction format RRR73#CHECK-INST: xsr a2, ibreaka174#CHECK: encoding: [0x20,0x81,0x61]75xsr a2,ibreaka176 77#Instruction format RRR78#CHECK-INST: xsr a2, ibreaka179#CHECK: encoding: [0x20,0x81,0x61]80xsr.ibreaka1 a281 82#Instruction format RRR83#CHECK-INST: xsr a2, ibreaka184#CHECK: encoding: [0x20,0x81,0x61]85xsr a2, 12986 87#Instruction format RRR88#CHECK-INST: xsr a2, dbreaka089#CHECK: encoding: [0x20,0x90,0x61]90xsr a2,dbreaka091 92#Instruction format RRR93#CHECK-INST: xsr a2, dbreaka094#CHECK: encoding: [0x20,0x90,0x61]95xsr.dbreaka0 a296 97#Instruction format RRR98#CHECK-INST: xsr a2, dbreaka099#CHECK: encoding: [0x20,0x90,0x61]100xsr a2, 144101 102#Instruction format RRR103#CHECK-INST: xsr a2, dbreaka1104#CHECK: encoding: [0x20,0x91,0x61]105xsr a2,dbreaka1106 107#Instruction format RRR108#CHECK-INST: xsr a2, dbreaka1109#CHECK: encoding: [0x20,0x91,0x61]110xsr.dbreaka1 a2111 112#Instruction format RRR113#CHECK-INST: xsr a2, dbreaka1114#CHECK: encoding: [0x20,0x91,0x61]115xsr a2, 145116 117#Instruction format RRR118#CHECK-INST: xsr a2, dbreakc0119#CHECK: encoding: [0x20,0xa0,0x61]120xsr a2,dbreakc0121 122#Instruction format RRR123#CHECK-INST: xsr a2, dbreakc0124#CHECK: encoding: [0x20,0xa0,0x61]125xsr.dbreakc0 a2126 127#Instruction format RRR128#CHECK-INST: xsr a2, dbreakc0129#CHECK: encoding: [0x20,0xa0,0x61]130xsr a2, 160131 132#Instruction format RRR133#CHECK-INST: xsr a2, dbreakc1134#CHECK: encoding: [0x20,0xa1,0x61]135xsr a2,dbreakc1136 137#Instruction format RRR138#CHECK-INST: xsr a2, dbreakc1139#CHECK: encoding: [0x20,0xa1,0x61]140xsr.dbreakc1 a2141 142#Instruction format RRR143#CHECK-INST: xsr a2, dbreakc1144#CHECK: encoding: [0x20,0xa1,0x61]145xsr a2, 161146 147#Instruction format RRR148#CHECK-INST: xsr a2, ibreakenable149#CHECK: encoding: [0x20,0x60,0x61]150xsr a2,ibreakenable151 152#Instruction format RRR153#CHECK-INST: xsr a2, ibreakenable154#CHECK: encoding: [0x20,0x60,0x61]155xsr.ibreakenable a2156 157#Instruction format RRR158#CHECK-INST: xsr a2, ibreakenable159#CHECK: encoding: [0x20,0x60,0x61]160xsr a2, 96161 162#Instruction format RRR163#CHECK-INST: rsr a2, debugcause164#CHECK: encoding: [0x20,0xe9,0x03]165rsr a2,debugcause166 167#Instruction format RRR168#CHECK-INST: rsr a2, debugcause169#CHECK: encoding: [0x20,0xe9,0x03]170rsr.debugcause a2171 172#Instruction format RRR173#CHECK-INST: rsr a2, debugcause174#CHECK: encoding: [0x20,0xe9,0x03]175rsr a2, 233176 177#Instruction format RRR178#CHECK-INST: xsr a2, ddr179#CHECK: encoding: [0x20,0x68,0x61]180xsr a2,ddr181 182#Instruction format RRR183#CHECK-INST: xsr a2, ddr184#CHECK: encoding: [0x20,0x68,0x61]185xsr.ddr a2186 187#Instruction format RRR188#CHECK-INST: xsr a2, ddr189#CHECK: encoding: [0x20,0x68,0x61]190xsr a2, 104191