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1# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s2 3---4name: invalid_reg_sequence5tracksRegLiveness: true6body: |7 bb.0:8 %0:vgpr_32 = IMPLICIT_DEF9 %1:vgpr_32 = IMPLICIT_DEF10 11 ; No operands12 ; CHECK: *** Bad machine code: Too few operands ***13 REG_SEQUENCE14 15 ; Only dest operand16 ; CHECK: *** Bad machine code: Too few operands ***17 %2:vreg_64 = REG_SEQUENCE18 19 ; Missing destination20 ; CHECK: *** Bad machine code: Explicit definition marked as use ***21 REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub122 23 ; Missing subreg operand24 ; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE ***25 %3:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %126 27 ; Missing register operand28 ; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE ***29 %4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %subreg.sub130 31 ; Physreg destination32 ; CHECK: *** Bad machine code: REG_SEQUENCE does not support physical register results ***33 $vgpr0_vgpr1 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub134 35 ; Subreg in destination36 ; CHECK: *** Bad machine code: Invalid subreg result for REG_SEQUENCE ***37 %5.sub0_sub1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub138 39 ; All operands are registers40 ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***41 %6:vreg_64 = REG_SEQUENCE %0, %142 43 ; Register and subreg index operand order swapped44 ; CHECK: *** Bad machine code: Invalid register operand for REG_SEQUENCE ***45 ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***46 %7:vreg_64 = REG_SEQUENCE %subreg.sub0, %0, %subreg.sub1, %147 48 ; Invalid subreg index constants49 ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***50 ; CHECK: - instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.9999951 ; CHECK-NEXT: operand 2: 052 53 ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***54 ; CHECK: instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.9999955 ; CHECK-NEXT: operand 4: 9999956 %8:vreg_64 = REG_SEQUENCE %0, 0, %1, 9999957 58...59