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1# REQUIRES: aarch64-registered-target2# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s3 4name: test5legalized: true6regBankSelected: false7body: |8 bb.0:9 liveins: $w0, $w110 %bank:gpr(s32) = COPY $w011 %class:gpr32(s32) = COPY $w112 13 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***14 ; CHECK: instruction: %bank_mismatch:fpr(s32) = G_ASSERT_ZEXT %bank:gpr, 1615 %bank_mismatch:fpr(s32) = G_ASSERT_ZEXT %bank, 1616 17 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT source and destination register classes must match ***18 ; CHECK: instruction: %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_ZEXT %class:gpr32, 1619 %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_ZEXT %class, 1620 21 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***22 ; CHECK: instruction: %class_mismatch_fpr:fpr32(s32) = G_ASSERT_ZEXT %class:gpr32, 1623 %class_mismatch_fpr:fpr32(s32) = G_ASSERT_ZEXT %class, 1624 25 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT source and destination register classes must match ***26 ; CHECK: instruction: %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_ZEXT %bank:gpr, 1627 %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_ZEXT %bank, 1628 29 ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***30 ; CHECK: instruction: %implicit_physreg:gpr(s32) = G_ASSERT_ZEXT %class:gpr32, 16, implicit-def $w031 %implicit_physreg:gpr(s32) = G_ASSERT_ZEXT %class, 16, implicit-def $w032 33 %nothing:_(s32) = G_IMPLICIT_DEF34 35 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***36 ; CHECK: %only_dst_has_bank:gpr(s32) = G_ASSERT_ZEXT %nothing:_, 437 %only_dst_has_bank:gpr(s32) = G_ASSERT_ZEXT %nothing, 438 39 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***40 ; CHECK: %only_dst_has_class:gpr32all(s32) = G_ASSERT_ZEXT %nothing:_, 441 %only_dst_has_class:gpr32all(s32) = G_ASSERT_ZEXT %nothing, 442