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1// RUN: llvm-tblgen -gen-subtarget -DCORRECT -I %p/../../include %s 2>&1 | \2// RUN: FileCheck %s --check-prefix=CORRECT3 4// RUN: not llvm-tblgen -gen-subtarget -DWRONG_SIZE -I %p/../../include %s 2>&1 | \5// RUN: FileCheck %s --check-prefix=WRONG_SIZE6 7// RUN: not llvm-tblgen -gen-subtarget -DWRONG_VALUE -I %p/../../include %s 2>&1 | \8// RUN: FileCheck %s --check-prefix=WRONG_VALUE9 10// RUN: not llvm-tblgen -gen-subtarget -DNEGATIVE_INVALID -I %p/../../include %s 2>&1 | \11// RUN: FileCheck %s --check-prefix=NEGATIVE_INVALID12 13// Make sure that AcquireAtCycle in WriteRes is used to generate the14// correct data.15 16include "llvm/Target/Target.td"17 18def MyTarget : Target;19 20let BufferSize = 0 in {21def ResX0 : ProcResource<1>; // X022def ResX1 : ProcResource<1>; // X123def ResX2 : ProcResource<1>; // X224}25 26let OutOperandList = (outs), InOperandList = (ins) in {27 def Inst_A : Instruction;28 def Inst_B : Instruction;29 def Inst_C : Instruction;30}31 32let CompleteModel = 0 in {33 def SchedModel_A: SchedMachineModel;34}35 36def WriteInst_A : SchedWrite;37def WriteInst_B : SchedWrite;38def WriteInst_C : SchedWrite;39 40let SchedModel = SchedModel_A in {41// Check the generated data when there are no semantic issues.42#ifdef CORRECT43// CORRECT-LABEL: llvm::MCWriteProcResEntry MyTargetWriteProcResTable[] = {44// CORRECT-NEXT: { 0, 0, 0 }, // Invalid45def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {46// CORRECT-NEXT: { 1, 2, 0}, // #147// CORRECT-NEXT: { 2, 4, 1}, // #248// CORRECT-NEXT: { 3, 3, 2}, // #349 let ReleaseAtCycles = [2, 4, 3];50 let AcquireAtCycles = [0, 1, 2];51}52def : WriteRes<WriteInst_B, [ResX2]> {53// If unspecified, AcquireAtCycle is set to 0.54// CORRECT-NEXT: { 3, 1, 0}, // #455 let ReleaseAtCycles = [1];56}57def : WriteRes<WriteInst_C, [ResX0]> {58// AcquireAtCycle and ReleaseAtCycle are allowed to be the same.59// CORRECT-NEXT: { 1, 0, 0} // #560 let ReleaseAtCycles = [0];61}62#endif // CORRECT63 64#ifdef WRONG_SIZE65// WRONG_SIZE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(AcquireAtCycles) != size(ProcResources): 2 vs 366def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {67 let ReleaseAtCycles = [2, 4, 3];68 let AcquireAtCycles = [0, 1];69}70#endif71 72#ifdef WRONG_VALUE73// WRONG_VALUE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: AcquireAtCycles <= ReleaseAtCycles must hold74def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {75 let ReleaseAtCycles = [2, 4, 3];76 let AcquireAtCycles = [0, 1, 8];77}78#endif79 80#ifdef NEGATIVE_INVALID81// NEGATIVE_INVALID: AcquireAtCycle.td:[[@LINE+1]]:1: error: Invalid value: AcquireAtCycle must be a non-negative value.82def : WriteRes<WriteInst_A, [ResX0]> {83 let ReleaseAtCycles = [2];84 let AcquireAtCycles = [-1];85}86#endif87 88def : InstRW<[WriteInst_A], (instrs Inst_A)>;89def : InstRW<[WriteInst_B], (instrs Inst_B)>;90def : InstRW<[WriteInst_C], (instrs Inst_C)>;91}92 93def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;94 95