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1// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o - 2>&1 >/dev/null | FileCheck %s --check-prefix=CHECK2include "llvm/Target/Target.td"3 4// This file tests that when using `isArtificial` for subregisters in5// combination with `CoveredBySubRegs`, that TableGen infers the6// correct register classes, subregisters and lane masks, especially7// when the registers (that consist partially from artificial subregs)8// are used in tuples.9//10// The register hierarchy that this test implements is:11//12// ssub_hi ssub13// \ /14// dsub15// dsub_hi /16// \ /17// qsub18//19// Where the _hi parts are artificial and where subregs ssub, dsub and qsub20// are all addressable as real registers.21//22// These are then used in {S0, S1, S2}, {D0, D1, D2} and {Q0, Q1, Q2},23// from which tuples are created.24 25class MyReg<string n, list<Register> subregs = []>26 : Register<n> {27 let Namespace = "Test";28 let SubRegs = subregs;29}30 31class MyClass<int size, list<ValueType> types, dag registers>32 : RegisterClass<"Test", types, size, registers> {33 let Size = size;34}35 36def ssub : SubRegIndex< 32, 0>;37def ssub_hi : SubRegIndex< 32, 32>;38def dsub : SubRegIndex< 64, 0>;39def dsub_hi : SubRegIndex< 64, 64>;40def qsub : SubRegIndex<128, 0>;41 42def S0 : MyReg<"s0">;43def S1 : MyReg<"s1">;44def S2 : MyReg<"s2">;45 46let isArtificial = 1 in {47def S0_HI : MyReg<"s0_hi">;48def S1_HI : MyReg<"s1_hi">;49def S2_HI : MyReg<"s2_hi">;50 51def D0_HI : MyReg<"D0_hi">;52def D1_HI : MyReg<"D1_hi">;53def D2_HI : MyReg<"D2_hi">;54}55 56let SubRegIndices = [ssub, ssub_hi], CoveredBySubRegs = 1 in {57def D0 : MyReg<"d0", [S0, S0_HI]>;58def D1 : MyReg<"d1", [S1, S1_HI]>;59def D2 : MyReg<"d2", [S2, S2_HI]>;60}61 62let SubRegIndices = [dsub, dsub_hi], CoveredBySubRegs = 1 in {63def Q0 : MyReg<"q0", [D0, D0_HI]>;64def Q1 : MyReg<"q1", [D1, D1_HI]>;65def Q2 : MyReg<"q2", [D2, D2_HI]>;66}67 68def SRegs : MyClass<32, [i32], (sequence "S%u", 0, 2)>;69def DRegs : MyClass<64, [i64], (sequence "D%u", 0, 2)>;70def QRegs : MyClass<128, [i128], (sequence "Q%u", 0, 2)>;71 72def dsub0 : SubRegIndex<64>;73def dsub1 : SubRegIndex<64>;74def dsub2 : SubRegIndex<64>;75 76def ssub0 : SubRegIndex<32>;77def ssub1 : ComposedSubRegIndex<dsub1, ssub>;78def ssub2 : ComposedSubRegIndex<dsub2, ssub>;79 80def STuples2 : RegisterTuples<[ssub0, ssub1],81 [(shl SRegs, 0), (shl SRegs, 1)]>;82def STuplesRC2 : MyClass<64, [untyped], (add STuples2)>;83 84def DTuples2 : RegisterTuples<[dsub0, dsub1],85 [(shl DRegs, 0), (shl DRegs, 1)]>;86def DTuplesRC2 : MyClass<128, [untyped], (add DTuples2)>;87 88def STuples3 : RegisterTuples<[ssub0, ssub1, ssub2],89 [(shl SRegs, 0), (shl SRegs, 1), (shl SRegs, 2)]>;90def STuplesRC3 : MyClass<96, [untyped], (add STuples3)>;91 92def DTuples3 : RegisterTuples<[dsub0, dsub1, dsub2],93 [(shl DRegs, 0), (shl DRegs, 1), (shl DRegs, 2)]>;94def DTuplesRC3 : MyClass<192, [untyped], (add DTuples3)>;95 96def TestTarget : Target;97 98// CHECK: RegisterClass SRegs:99// CHECK: LaneMask: 0000000000000001100// CHECK: HasDisjunctSubRegs: 0101// CHECK: CoveredBySubRegs: 0102// CHECK: Regs: S0 S1 S2103// CHECK: SubClasses: SRegs104// CHECK: SuperClasses:105//106// CHECK: RegisterClass DRegs:107// CHECK: LaneMask: 0000000000000044108// CHECK: HasDisjunctSubRegs: 1109// CHECK: CoveredBySubRegs: 1110// CHECK: Regs: D0 D1 D2111// CHECK: SubClasses: DRegs112// CHECK: SuperClasses:113//114// CHECK: RegisterClass QRegs:115// CHECK: LaneMask: 0000000000000045116// CHECK: HasDisjunctSubRegs: 1117// CHECK: CoveredBySubRegs: 1118// CHECK: Regs: Q0 Q1 Q2119// CHECK: SubClasses: QRegs120// CHECK: SuperClasses:121//122// CHECK: SubRegIndex dsub:123// CHECK-NEXT: LaneMask: 0000000000000044124// CHECK: SubRegIndex dsub0:125// CHECK-NEXT: LaneMask: 0000000000000044126// CHECK: SubRegIndex dsub1:127// CHECK-NEXT: LaneMask: 0000000000000090128// CHECK: SubRegIndex dsub2:129// CHECK-NEXT: LaneMask: 0000000000000120130// CHECK: SubRegIndex dsub_hi:131// CHECK-NEXT: LaneMask: 0000000000000001132// CHECK: SubRegIndex ssub:133// CHECK-NEXT: LaneMask: 0000000000000004134// CHECK: SubRegIndex ssub0:135// CHECK-NEXT: LaneMask: 0000000000000008136// CHECK: SubRegIndex ssub1:137// CHECK-NEXT: LaneMask: 0000000000000010138// CHECK: SubRegIndex ssub2:139// CHECK-NEXT: LaneMask: 0000000000000020140// CHECK: SubRegIndex ssub_hi:141// CHECK-NEXT: LaneMask: 0000000000000040142// CHECK: SubRegIndex dsub1_then_ssub_hi:143// CHECK-NEXT: LaneMask: 0000000000000080144// CHECK: SubRegIndex dsub2_then_ssub_hi:145// CHECK-NEXT: LaneMask: 0000000000000100146// CHECK: SubRegIndex ssub_ssub1:147// CHECK-NEXT: LaneMask: 0000000000000014148// CHECK: SubRegIndex dsub0_dsub1:149// CHECK-NEXT: LaneMask: 00000000000000D4150// CHECK: SubRegIndex dsub1_dsub2:151// CHECK-NEXT: LaneMask: 00000000000001B0152// CHECK: SubRegIndex ssub_ssub1_ssub2:153// CHECK-NEXT: LaneMask: 0000000000000034154// CHECK: SubRegIndex ssub1_ssub2:155// CHECK-NEXT: LaneMask: 0000000000000030156// CHECK: SubRegIndex ssub0_ssub1:157// CHECK-NEXT: LaneMask: 0000000000000018158 159// CHECK: Register D0:160// CHECK: CoveredBySubregs: 1161// CHECK: HasDisjunctSubRegs: 1162// CHECK: SubReg ssub = S0163// CHECK: SubReg ssub_hi = S0_HI164//165// CHECK: Register Q0:166// CHECK: CoveredBySubregs: 1167// CHECK: HasDisjunctSubRegs: 1168// CHECK: SubReg dsub = D0169// CHECK: SubReg dsub_hi = D0_HI170// CHECK: SubReg ssub = S0171// CHECK: SubReg ssub_hi = S0_HI172//173// CHECK: Register S0:174// CHECK: CoveredBySubregs: 0175// CHECK: HasDisjunctSubRegs: 0176//177// CHECK: Register D0_D1:178// CHECK: CoveredBySubregs: 1179// CHECK: HasDisjunctSubRegs: 1180// CHECK: SubReg dsub0 = D0181// CHECK: SubReg dsub1 = D1182// CHECK: SubReg ssub = S0183// CHECK: SubReg ssub1 = S1184// CHECK: SubReg ssub_hi = S0_HI185// CHECK: SubReg dsub1_then_ssub_hi = S1_HI186// CHECK: SubReg ssub_ssub1 = S0_S1187//188// CHECK: Register D0_D1_D2:189// CHECK: CoveredBySubregs: 1190// CHECK: HasDisjunctSubRegs: 1191// CHECK: SubReg dsub0 = D0192// CHECK: SubReg dsub1 = D1193// CHECK: SubReg dsub2 = D2194// CHECK: SubReg ssub = S0195// CHECK: SubReg ssub1 = S1196// CHECK: SubReg ssub2 = S2197// CHECK: SubReg ssub_hi = S0_HI198// CHECK: SubReg dsub1_then_ssub_hi = S1_HI199// CHECK: SubReg dsub2_then_ssub_hi = S2_HI200// CHECK: SubReg ssub_ssub1 = S0_S1201// CHECK: SubReg dsub0_dsub1 = D0_D1202// CHECK: SubReg dsub1_dsub2 = D1_D2203// CHECK: SubReg ssub_ssub1_ssub2 = S0_S1_S2204// CHECK: SubReg ssub1_ssub2 = S1_S2205//206// CHECK: Register S0_S1:207// CHECK: CoveredBySubregs: 1208// CHECK: HasDisjunctSubRegs: 1209// CHECK: SubReg ssub0 = S0210// CHECK: SubReg ssub1 = S1211//212// CHECK: Register S0_S1_S2:213// CHECK: CoveredBySubregs: 1214// CHECK: HasDisjunctSubRegs: 1215// CHECK: SubReg ssub0 = S0216// CHECK: SubReg ssub1 = S1217// CHECK: SubReg ssub2 = S2218// CHECK: SubReg ssub1_ssub2 = S1_S2219// CHECK: SubReg ssub0_ssub1 = S0_S1220