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1// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \2// RUN: FileCheck --check-prefix=COMPRESS %s3 4// Check that combining conditions in AssemblerPredicate generates the correct5// output when using both the (all_of) AND operator, and the (any_of) OR6// operator in the RISC-V specific instruction compressor.7 8include "llvm/Target/Target.td"9 10def archInstrInfo : InstrInfo { }11def archAsmWriter : AsmWriter {12 int PassSubtarget = 1;13}14 15def arch : Target {16 let InstructionSet = archInstrInfo;17 let AssemblyWriters = [archAsmWriter];18}19 20let Namespace = "arch" in {21 def R0 : Register<"r0">;22}23def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;24 25class RVInst<int Opc, list<Predicate> Preds> : Instruction {26 let Size = 4;27 let OutOperandList = (outs);28 let InOperandList = (ins Regs:$r);29 field bits<32> Inst;30 let Inst = Opc;31 let AsmString = NAME # " $r";32 field bits<32> SoftFail = 0;33 let Predicates = Preds;34}35class RVInst16<int Opc, list<Predicate> Preds> : Instruction {36 let Size = 2;37 let OutOperandList = (outs);38 let InOperandList = (ins Regs:$r);39 field bits<16> Inst;40 let Inst = Opc;41 let AsmString = NAME # " $r";42 field bits<16> SoftFail = 0;43 let Predicates = Preds;44}45 46def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;47def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;48def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;49def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;50def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;51 52def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;53def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;54def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;55 56def BigInst : RVInst<1, [AsmPred1]>;57 58// COMPRESS-LABEL: static bool compressInst59// COMPRESS: case arch::BigInst60def SmallInst1 : RVInst16<1, []>;61def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;62// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&63// COMPRESS-NEXT: MI.getOperand(0).isReg() &&64// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {65// COMPRESS-NEXT: // SmallInst1 $r66 67def SmallInst2 : RVInst16<2, []>;68def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;69// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&70// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&71// COMPRESS-NEXT: MI.getOperand(0).isReg() &&72// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {73// COMPRESS-NEXT: // SmallInst2 $r74 75def SmallInst3 : RVInst16<2, []>;76def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;77// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&78// COMPRESS-NEXT: MI.getOperand(0).isReg() &&79// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {80// COMPRESS-NEXT: // SmallInst3 $r81 82def SmallInst4 : RVInst16<2, []>;83def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;84// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&85// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&86// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&87// COMPRESS-NEXT: MI.getOperand(0).isReg() &&88// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {89// COMPRESS-NEXT: // SmallInst4 $r90 91def SmallInst5 : RVInst16<2, []>;92def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;93// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&94// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&95// COMPRESS-NEXT: MI.getOperand(0).isReg() &&96// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {97// COMPRESS-NEXT: // SmallInst5 $r98 99// COMPRESS-LABEL: static bool uncompressInst100 101// COMPRESS-LABEL: static bool isCompressibleInst102 103// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&104// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&105// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {106// COMPRESS-NEXT: // SmallInst1 $r107 108// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&109// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&110// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&111// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {112// COMPRESS-NEXT: // SmallInst2 $r113 114// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&115// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&116// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {117// COMPRESS-NEXT: // SmallInst3 $r118 119// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&120// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&121// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&122// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&123// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {124// COMPRESS-NEXT: // SmallInst4 $r125 126// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&127// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&128// COMPRESS-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&129// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {130// COMPRESS-NEXT: // SmallInst5 $r131