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1// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../../include %s 2>&1 | FileCheck %s2 3include "llvm/Target/Target.td"4 5def ArchInstrInfo : InstrInfo { }6def ArchAsmWriter : AsmWriter {7 int PassSubtarget = 1;8}9 10def Arch : Target {11 let InstructionSet = ArchInstrInfo;12 let AssemblyWriters = [ArchAsmWriter];13}14 15def Reg0 : Register<"reg0"> {16 let HWEncoding{4-0} = 0;17}18def Reg1 : Register<"reg1"> {19 let HWEncoding{4-0} = 1;20}21 22def Regs : RegisterClass<"Arch", [i32], 32, (add Reg0, Reg1)>;23def RegsC : RegisterClass<"Arch", [i32], 32, (sub Regs, Reg0)>;24 25def simm6 : Operand<i32>, ImmLeaf<i32, [{return isInt<6>(Imm);}]> {26 let MCOperandPredicate = [{27 int64_t Imm;28 if (!MCOp.evaluateAsConstantImm(Imm))29 return false;30 return isInt<6>(Imm);31 }];32}33 34def simm12 : Operand<i32>, ImmLeaf<i32, [{return isInt<12>(Imm);}]> {35 let MCOperandPredicate = [{36 int64_t Imm;37 if (!MCOp.evaluateAsConstantImm(Imm))38 return false;39 return isInt<12>(Imm);40 }];41}42 43def MemOpnd : Operand<iPTR> {44 let MIOperandInfo = (ops Regs, simm12);45}46 47def MemOpndC : Operand<iPTR> {48 let MIOperandInfo = (ops RegsC, simm6);49}50 51def BigInst : Instruction {52 let Namespace = "MyNS";53 let OutOperandList = (outs Regs:$dst);54 let InOperandList = (ins MemOpnd:$addr);55 let Size = 4;56 let AsmString = "big $dst, $addr";57}58 59def SmallInst : Instruction {60 let Namespace = "MyNS";61 let OutOperandList = (outs RegsC:$dst);62 let InOperandList = (ins MemOpndC:$addr);63 let Size = 2;64 let AsmString = "small $dst, $addr";65}66 67def : CompressPat<(BigInst RegsC:$dst, RegsC:$src, simm6:$imm),68 (SmallInst RegsC:$dst, RegsC:$src, simm6:$imm)>;69 70def BigInst2 : Instruction {71 let Namespace = "MyNS";72 let OutOperandList = (outs Regs:$dst);73 let InOperandList = (ins MemOpnd:$addr);74 let Size = 4;75 let AsmString = "big $dst, $addr";76}77 78def SmallInst2 : Instruction {79 let Namespace = "MyNS";80 let OutOperandList = (outs RegsC:$dst);81 let InOperandList = (ins RegsC:$src, simm6:$imm);82 let Size = 2;83 let AsmString = "small $dst, $src, $imm";84}85 86def : CompressPat<(BigInst2 RegsC:$dst, RegsC:$src, simm6:$imm),87 (SmallInst2 RegsC:$dst, RegsC:$src, simm6:$imm)>;88 89def BigInst3 : Instruction {90 let Namespace = "MyNS";91 let OutOperandList = (outs Regs:$dst);92 let InOperandList = (ins Regs:$src, simm12:$imm);93 let Size = 4;94 let AsmString = "big $dst, $src, $imm";95}96 97def SmallInst3 : Instruction {98 let Namespace = "MyNS";99 let OutOperandList = (outs RegsC:$dst);100 let InOperandList = (ins MemOpndC:$addr);101 let Size = 2;102 let AsmString = "small $dst, $addr";103}104 105def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),106 (SmallInst3 RegsC:$dst, RegsC:$src, simm6:$imm)>;107 108// CHECK-LABEL: ArchValidateMCOperandForCompress109// CHECK: // simm6110// CHECK: return isInt<6>(Imm);111 112// CHECK-LABEL: compressInst113// CHECK: case Arch::BigInst114// CHECK-NEXT: if (MI.getOperand(0).isReg() &&115// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&116// CHECK-NEXT: MI.getOperand(1).isReg() &&117// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&118// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) {119// CHECK-NEXT: // small $dst, $addr120// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst);121// CHECK-NEXT: // Operand: dst122// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));123// CHECK-NEXT: // Operand: addr124// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));125// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));126// CHECK-NEXT: OutInst.setLoc(MI.getLoc());127// CHECK-NEXT: return true;128// CHECK-NEXT: } // if129// CHECK: case Arch::BigInst2130// CHECK-NEXT: if (MI.getOperand(0).isReg() &&131// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&132// CHECK-NEXT: MI.getOperand(1).isReg() &&133// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&134// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) {135// CHECK-NEXT: // small $dst, $src, $imm136// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst2);137// CHECK-NEXT: // Operand: dst138// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));139// CHECK-NEXT: // Operand: src140// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));141// CHECK-NEXT: // Operand: imm142// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));143// CHECK-NEXT: OutInst.setLoc(MI.getLoc());144// CHECK-NEXT: return true;145// CHECK-NEXT: } // if146// CHECK: case Arch::BigInst3147// CHECK-NEXT: if (MI.getOperand(0).isReg() &&148// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&149// CHECK-NEXT: MI.getOperand(1).isReg() &&150// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&151// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) {152// CHECK-NEXT: // small $dst, $addr153// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst3);154// CHECK-NEXT: // Operand: dst155// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));156// CHECK-NEXT: // Operand: addr157// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));158// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));159// CHECK-NEXT: OutInst.setLoc(MI.getLoc());160// CHECK-NEXT: return true;161// CHECK-NEXT: } // if162 163// CHECK-LABEL: ArchValidateMCOperandForUncompress164// CHECK: // simm6165// CHECK: return isInt<6>(Imm);166 167// CHECK-LABEL: uncompressInst168// CHECK: case Arch::SmallInst:169// CHECK-NEXT: if (MI.getOperand(0).isReg() &&170// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&171// CHECK-NEXT: MI.getOperand(1).isReg() &&172// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&173// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) &&174// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */))175// CHECK-NEXT: // big $dst, $addr176// CHECK-NEXT: OutInst.setOpcode(Arch::BigInst);177// CHECK-NEXT: // Operand: dst178// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));179// CHECK-NEXT: // Operand: addr180// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));181// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));182// CHECK-NEXT: OutInst.setLoc(MI.getLoc());183// CHECK-NEXT: return true;184// CHECK-NEXT: } // if185// CHECK: case Arch::SmallInst2:186// CHECK-NEXT: if (MI.getOperand(0).isReg() &&187// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&188// CHECK-NEXT: MI.getOperand(1).isReg() &&189// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&190// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) &&191// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) {192// CHECK-NEXT: // big $dst, $addr193// CHECK-NEXT: OutInst.setOpcode(Arch::BigInst2);194// CHECK-NEXT: // Operand: dst195// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));196// CHECK-NEXT: // Operand: addr197// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));198// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));199// CHECK-NEXT: OutInst.setLoc(MI.getLoc());200// CHECK-NEXT: return true;201// CHECK-NEXT: } // if202// CHECK: case Arch::SmallInst3:203// CHECK-NEXT: if (MI.getOperand(0).isReg() &&204// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&205// CHECK-NEXT: MI.getOperand(1).isReg() &&206// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&207// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) &&208// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) {209// CHECK-NEXT: // big $dst, $src, $imm210// CHECK-NEXT: OutInst.setOpcode(Arch::BigInst3);211// CHECK-NEXT: // Operand: dst212// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));213// CHECK-NEXT: // Operand: src214// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));215// CHECK-NEXT: // Operand: imm216// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));217// CHECK-NEXT: OutInst.setLoc(MI.getLoc());218// CHECK-NEXT: return true;219// CHECK-NEXT: } // if220 221// CHECK-LABEL: ArchValidateMachineOperand222// CHECK: // simm6223// CHECK: return isInt<6>(Imm);224 225// CHECK-LABEL: isCompressibleInst226// CHECK: case Arch::BigInst: {227// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&228// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&229// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&230// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&231// CHECK-NEXT: MI.getOperand(2).isImm() &&232// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) {233// CHECK-NEXT: // small $dst, $addr234// CHECK-NEXT: // Operand: dst235// CHECK-NEXT: // Operand: addr236// CHECK-NEXT: return true;237// CHECK-NEXT: } // if238// CHECK: case Arch::BigInst2: {239// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&240// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&241// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&242// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&243// CHECK-NEXT: MI.getOperand(2).isImm() &&244// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) {245// CHECK-NEXT: // small $dst, $src, $imm246// CHECK-NEXT: // Operand: dst247// CHECK-NEXT: // Operand: src248// CHECK-NEXT: // Operand: imm249// CHECK-NEXT: return true;250// CHECK-NEXT: } // if251// CHECK: case Arch::BigInst3: {252// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&253// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&254// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&255// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&256// CHECK-NEXT: MI.getOperand(2).isImm() &&257// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) {258// CHECK-NEXT: // small $dst, $addr259// CHECK-NEXT: // Operand: dst260// CHECK-NEXT: // Operand: addr261// CHECK-NEXT: return true;262// CHECK-NEXT: } // if263