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1// RUN: llvm-tblgen -gen-disassembler -use-fn-table-in-decode-to-mcinst -I %p/../../../include %s | FileCheck %s2 3include "llvm/Target/Target.td"4 5def archInstrInfo : InstrInfo { }6 7def arch : Target {8 let InstructionSet = archInstrInfo;9}10 11let Namespace = "arch" in {12 def R0 : Register<"r0">;13 def R1 : Register<"r1">;14 def R2 : Register<"r2">;15 def R3 : Register<"r3">;16}17def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3)>;18 19class TestInstruction : Instruction {20 let Size = 1;21 let OutOperandList = (outs);22 field bits<8> Inst;23 field bits<8> SoftFail = 0;24}25 26// Define instructions to generate 4 cases in decodeToMCInst.27// Lower 2 bits define the number of operands. Each register operand28// needs 2 bits to encode.29 30// An instruction with no inputs. Encoded with lower 2 bits = 0 and upper31// 6 bits = 0 as well.32def Inst0 : TestInstruction {33 let Inst = 0x0;34 let InOperandList = (ins);35 let AsmString = "Inst0";36}37 38// An instruction with a single input. Encoded with lower 2 bits = 1 and the39// single input in bits 2-3.40def Inst1 : TestInstruction {41 bits<2> r0;42 let Inst{1-0} = 1;43 let Inst{3-2} = r0;44 let InOperandList = (ins Regs:$r0);45 let AsmString = "Inst1";46}47 48// An instruction with two inputs. Encoded with lower 2 bits = 2 and the49// inputs in bits 2-3 and 4-5.50def Inst2 : TestInstruction {51 bits<2> r0;52 bits<2> r1;53 let Inst{1-0} = 2;54 let Inst{3-2} = r0;55 let Inst{5-4} = r1;56 let InOperandList = (ins Regs:$r0, Regs:$r1);57 let AsmString = "Inst2";58}59 60// An instruction with three inputs. Encoded with lower 2 bits = 3 and the61// inputs in bits 2-3 and 4-5 and 6-7.62def Inst3 : TestInstruction {63 bits<2> r0;64 bits<2> r1;65 bits<2> r2;66 let Inst{1-0} = 3;67 let Inst{3-2} = r0;68 let Inst{5-4} = r1;69 let Inst{7-6} = r2;70 let InOperandList = (ins Regs:$r0, Regs:$r1, Regs:$r2);71 let AsmString = "Inst3";72}73 74// CHECK-LABEL: DecodeStatus decodeFn_0(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)75// CHECK-LABEL: DecodeStatus decodeFn_1(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)76// CHECK-LABEL: DecodeStatus decodeFn_2(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)77// CHECK-LABEL: DecodeStatus decodeFn_3(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)78// CHECK-LABEL: decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)79// CHECK: static constexpr DecodeFnTy decodeFnTable[]80// CHECK-NEXT: decodeFn_0,81// CHECK-NEXT: decodeFn_1,82// CHECK-NEXT: decodeFn_2,83// CHECK-NEXT: decodeFn_3,84// CHECK: return decodeFnTable[Idx](S, insn, MI, Address, Decoder, DecodeComplete)85