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1// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s --check-prefixes=CHECK2 3include "llvm/Target/Target.td"4 5def ArchInstrInfo : InstrInfo { }6 7def Arch : Target {8 let InstructionSet = ArchInstrInfo;9}10 11def Reg : Register<"reg">;12 13def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;14 15def GR64 : RegisterOperand<RegClass>;16 17class MyMemOperand<dag sub_ops> : Operand<iPTR> {18 let MIOperandInfo = sub_ops;19 dag Base;20 dag Extension;21}22 23def MemOp16: MyMemOperand<(ops GR64:$reg, i16imm:$offset)>;24 25def MemOp32: MyMemOperand<(ops GR64:$reg, i32imm:$offset)>;26 27class MyVarInst<MyMemOperand memory_op> : Instruction {28 dag Inst;29 30 let OutOperandList = (outs GR64:$dst);31 let InOperandList = (ins memory_op:$src);32}33 34def FOO16 : MyVarInst<MemOp16> {35 let Inst = (ascend36 (descend (operand "$dst", 3), 0b01000, (operand "$src.reg", 3)),37 (slice "$src.offset", 15, 0, (decoder "myCustomDecoder"))38 );39}40def FOO32 : MyVarInst<MemOp32> {41 let Inst = (ascend42 (descend (operand "$dst", 3), 0b01001,43 (operand "$src.reg", 3, (decoder "myCustomDecoder"))),44 (slice "$src.offset", 31, 16),45 (slice "$src.offset", 15, 0)46 );47}48 49// Instruction length table50// CHECK: InstrLenTable51// CHECK: 27,52// CHECK-NEXT: 43,53// CHECK-NEXT: };54 55// CHECK-LABEL: static const uint8_t DecoderTable43[15] = {56// CHECK-NEXT: OPC_SwitchField, 3, 5, // 0: switch Inst[7:3] {57// CHECK-NEXT: 8, 4, // 3: case 0x8: {58// CHECK-NEXT: OPC_Decode, {{[0-9, ]+}}, 0, // 5: decode to FOO16 using decoder 059// CHECK-NEXT: // 5: }60// CHECK-NEXT: 9, 0, // 9: case 0x9: {61// CHECK-NEXT: OPC_Decode, {{[0-9, ]+}}, 1, // 11: decode to FOO32 using decoder 162// CHECK-NEXT: // 11: }63// CHECK-NEXT: // 11: } // switch Inst[7:3]64// CHECK-NEXT: };65 66// CHECK: case 0:67// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);68// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }69// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);70// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }71// CHECK-NEXT: tmp = fieldFromInstruction(insn, 11, 16);72// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }73// CHECK-NEXT: return S;74// CHECK-NEXT: case 1:75// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);76// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }77// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);78// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }79// CHECK-NEXT: tmp = 0x0;80// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 11, 16) << 16;81// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 27, 16);82// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));83// CHECK-NEXT: return S;84 85// CHECK-LABEL: case OPC_SwitchField: {86// CHECK: makeUp(insn, Start + Len);87 88// CHECK-LABEL: case OPC_CheckField: {89// CHECK: makeUp(insn, Start + Len);90 91// CHECK-LABEL: case OPC_Decode: {92// CHECK: Len = InstrLenTable[Opc];93// CHECK-NEXT: makeUp(insn, Len);94