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1// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t2// RUN: FileCheck %s < %t3 4include "llvm/Target/Target.td"5 6def MyTargetISA : InstrInfo;7def MyTarget : Target { let InstructionSet = MyTargetISA; }8 9def R0 : Register<"r0"> { let Namespace = "MyTarget"; }10def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;11 12def X0 : Register<"x0"> { let Namespace = "MyTarget"; }13def GPR64 : RegisterClass<"MyTarget", [i64], 64, (add X0)>;14 15class I<dag OOps, dag IOps, list<dag> Pat>16 : Instruction {17 let Namespace = "MyTarget";18 let OutOperandList = OOps;19 let InOperandList = IOps;20 let Pattern = Pat;21 let Size = 4;22 bits<32> Inst;23 bits<32> SoftFail;24}25 26// Assume there is a 2 bit encoding for the dst and src register.27def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {28 bits<2> dst;29 bits<2> src1;30 let Inst{31...4} = 0;31 let Inst{1...0} = dst;32 let Inst{3...2} = src1;33}34 35def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {36 bits<2> dst;37 bits<2> src1;38 let Inst{31...4} = 0;39 let Inst{1...0} = dst;40 let Inst{3...2} = src1;41}42 43def C : I<(outs GPR64:$dst), (ins GPR64:$src1), []> {44 bits<2> dst;45 bits<2> src1;46 let Inst{31...4} = 1;47 let Inst{1...0} = dst;48 let Inst{3...2} = src1;49}50 51def D : I<(outs GPR64:$dst), (ins GPR64:$src1), []> {52 bits<2> dst;53 bits<2> src1;54 let Inst{31...4} = 1;55 let Inst{1...0} = dst;56 let Inst{3...2} = src1;57}58 59// CHECK: Decoding Conflict:60// CHECK: ................................61// CHECK: 0000000000000000000000000000....62// CHECK: 0000000000000000000000000000____ A63// CHECK: 0000000000000000000000000000____ B64 65// CHECK: Decoding Conflict:66// CHECK: ................................67// CHECK: 0000000000000000000000000001....68// CHECK: 0000000000000000000000000001____ C69// CHECK: 0000000000000000000000000001____ D70 71// CHECK: Decoding conflict encountered72