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1// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s2 3include "llvm/Target/Target.td"4 5def R0 : Register<"r0">;6def RC : RegisterClass<"MyTarget", [i32], 32, (add R0)>;7 8def MyInstrInfo : InstrInfo;9 10def MyTarget : Target {11 let InstructionSet = MyInstrInfo;12}13 14// CHECK-LABEL: case 0:15// CHECK-NEXT: if (!Check(S, DecodeRCRegisterClass(MI, Decoder)))16// CHECK-NEXT: return MCDisassembler::Fail;17// CHECK-NEXT: tmp = fieldFromInstruction(insn, 2, 4);18// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));19// CHECK-NEXT: tmp = 0x0;20// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 0, 2);21// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 6, 2) << 2;22// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));23// CHECK-NEXT: tmp = 0x0;24// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));25// CHECK-NEXT: tmp = fieldFromInstruction(insn, 13, 2) << 1;26// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));27// CHECK-NEXT: tmp = 0x0;28// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 17, 1) << 1;29// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 19, 1) << 3;30// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));31// CHECK-NEXT: tmp = 0x5;32// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));33// CHECK-NEXT: tmp = 0x2;34// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 26, 2) << 2;35// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));36// CHECK-NEXT: tmp = 0xa;37// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 28, 1);38// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 30, 1) << 2;39// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));40// CHECK-NEXT: return S;41 42def I : Instruction {43 let OutOperandList = (outs RC:$op0);44 let InOperandList = (ins i32imm:$op1, i32imm:$op2, i32imm:$op3, i32imm:$op4,45 i32imm:$op5, i32imm:$op6, i32imm:$op7, i32imm:$op8);46 let Size = 4;47 bits<32> Inst;48 bits<0> op0; // no init, no variable parts49 bits<4> op1; // no init, 1 variable part50 bits<4> op2; // no init, 2 variable parts51 bits<4> op3 = 0b0000; // zero init, no variable parts52 bits<4> op4 = {0, ?, ?, 0}; // zero init, 1 variable part53 bits<4> op5 = {?, 0, ?, 0}; // zero init, 2 variable parts54 bits<4> op6 = 0b0101; // non-zero init, no variable parts55 bits<4> op7 = {?, ?, 1, 0}; // non-zero init, 1 variable part56 bits<4> op8 = {1, ?, 1, ?}; // non-zero init, 2 variable parts57 let Inst{5...2} = op1;58 let Inst{1...0} = op2{1...0};59 let Inst{7...6} = op2{3...2};60 let Inst{11...8} = op3;61 let Inst{15...12} = op4;62 let Inst{19...16} = op5;63 let Inst{23...20} = op6;64 let Inst{27...24} = op7;65 let Inst{31...28} = op8;66}67