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1// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../../include -I %p/../Common | FileCheck %s2 3include "llvm/Target/Target.td"4include "GlobalISelEmitterCommon.td"5 6// Boilerplate code for setting up some registers with subregs.7class MyReg<string n, list<Register> subregs = []>8 : Register<n> {9 let SubRegs = subregs;10}11 12class MyClass<int size, list<ValueType> types, dag registers>13 : RegisterClass<"Test", types, size, registers> {14 let Size = size;15}16 17def sub0 : SubRegIndex<16>;18def sub1 : SubRegIndex<16, 16>;19def S0 : MyReg<"s0">;20def S1 : MyReg<"s1">;21def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 1)>;22 23let SubRegIndices = [sub0, sub1] in {24def D0 : MyReg<"d0", [S0, S1]>;25}26 27def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 0)>;28def SOP : RegisterOperand<SRegs>;29def DOP : RegisterOperand<DRegs>;30def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>;31def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;32 33// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,34// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT),35// CHECK-NEXT: // MIs[0] DstI[dst]36// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,37// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),38// CHECK-NEXT: // MIs[0] src39// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,40// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID),41// CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] })42// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,43// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),44// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),45// CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src46// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,47// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,48// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),49// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),50// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src51// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,52// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),53// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]54// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,55// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,56// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,57// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,58// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),59// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID),60// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID),61// CHECK-NEXT: // GIR_Coverage, 0,62// CHECK-NEXT: GIR_EraseRootFromParent_Done,63def : Pat<(i32 (sext SOP:$src)),64 (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,65 (SUBSOME_INSN SOP:$src), sub1)>;66 67 68// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ZEXT),69// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),70// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),71// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,72// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,73// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,74// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,75// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),76// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID),77// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID),78// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN),79// Make sure operands are constrained when REG_SEQUENCE isn't the root instruction.80def : Pat<(i32 (zext SOP:$src)),81 (SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,82 (SUBSOME_INSN SOP:$src), sub1))>;83