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1// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../../include -I %p/../Common %s | FileCheck %s2 3include "llvm/Target/Target.td"4include "GlobalISelEmitterCommon.td"5 6def GPR : RegisterClass<"MyTarget", [i64], 64, (add R0)>;7def ANDI : I<(outs GPR:$dst), (ins GPR:$src1, i64imm:$src2), []>;8 9// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(59), // Rule ID 0 //10// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,11// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND),12// CHECK-NEXT: // MIs[0] DstI[dst]13// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,14// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),15// CHECK-NEXT: // MIs[0] rs116// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,17// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),18// CHECK-NEXT: // MIs[0] Operand 219// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,20// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(9223372036854775808u),21// CHECK-NEXT: // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] }) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] })22// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANDI),23// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]24// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs125// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(9223372036854775808u),26// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,27// CHECK-NEXT: // GIR_Coverage, 0,28// CHECK-NEXT: GIR_EraseRootFromParent_Done,29def : Pat<(and GPR:$rs1, 0x8000000000000000),30 (ANDI GPR:$rs1, 0x8000000000000000)>;31