183 lines · plain
1// This is to test the scenario where different HwMode attributes coexist.2// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o - 2>&1 >/dev/null | FileCheck %s --check-prefix=CHECK-REG3// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SUBTARGET4 5 6include "llvm/Target/Target.td"7 8def TestTargetInstrInfo : InstrInfo;9 10def TestTarget : Target {11 let InstructionSet = TestTargetInstrInfo;12}13 14def Feat1 : SubtargetFeature<"feat1", "HasFeat1", "true", "enable feature 1">;15def Feat2 : SubtargetFeature<"feat2", "HasFeat2", "true", "enable feature 2">;16 17def HasFeat1 : Predicate<"Subtarget->hasFeat1()">,18 AssemblerPredicate<(all_of Feat1)>;19def HasFeat2 : Predicate<"Subtarget->hasFeat2()">,20 AssemblerPredicate<(all_of Feat2)>;21 22def TestMode : HwMode<[HasFeat1]>;23def TestMode1 : HwMode<[HasFeat2]>;24def TestMode2 : HwMode<[HasFeat1, HasFeat2]>;25 26class MyReg<string n>27 : Register<n> {28 let Namespace = "Test";29}30 31class MyClass<int size, list<ValueType> types, dag registers>32 : RegisterClass<"Test", types, size, registers> {33 let Size = size;34}35 36def X0 : MyReg<"x0">;37def X1 : MyReg<"x1">;38def X2 : MyReg<"x2">;39def X3 : MyReg<"x3">;40def X4 : MyReg<"x4">;41def X5 : MyReg<"x5">;42def X6 : MyReg<"x6">;43def X7 : MyReg<"x7">;44def X8 : MyReg<"x8">;45def X9 : MyReg<"x9">;46def X10 : MyReg<"x10">;47def X11 : MyReg<"x11">;48def X12 : MyReg<"x12">;49def X13 : MyReg<"x13">;50def X14 : MyReg<"x14">;51def X15 : MyReg<"x15">;52 53def ValueModeVT : ValueTypeByHwMode<[DefaultMode, TestMode, TestMode1],54 [i32, i64, f32]>;55 56let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],57 [RegInfo<32,32,32>, RegInfo<64,64,64>]> in58def XRegs : MyClass<32, [ValueModeVT], (sequence "X%u", 0, 15)>;59 60def sub_even : SubRegIndex<32> {61 let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],62 [SubRegRange<32>, SubRegRange<64>]>;63}64def sub_odd : SubRegIndex<32, 32> {65 let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],66 [SubRegRange<32, 32>, SubRegRange<64, 64>]>;67}68 69def XPairs : RegisterTuples<[sub_even, sub_odd],70 [(decimate (rotl XRegs, 0), 2),71 (decimate (rotl XRegs, 1), 2)]>;72 73let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],74 [RegInfo<64,64,32>, RegInfo<128,128,64>]> in75def XPairsClass : MyClass<64, [untyped], (add XPairs)>;76 77// Modes who are not controlling Register related features will be manipulated78// the same as DefaultMode.79// CHECK-REG-LABEL: RegisterClass XRegs:80// CHECK-REG: SpillSize: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }81// CHECK-REG: SpillAlignment: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }82// CHECK-REG: Regs: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X1583 84// CHECK-REG-LABEL: RegisterClass XPairsClass:85// CHECK-REG: SpillSize: { Default:64 TestMode:128 TestMode1:64 TestMode2:64 }86// CHECK-REG: SpillAlignment: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }87// CHECK-REG: CoveredBySubRegs: 188// CHECK-REG: Regs: X0_X1 X2_X3 X4_X5 X6_X7 X8_X9 X10_X11 X12_X13 X14_X1589 90// CHECK-REG-LABEL: SubRegIndex sub_even:91// CHECK-REG: Offset: { Default:0 TestMode:0 TestMode1:0 TestMode2:0 }92// CHECK-REG: Size: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }93// CHECK-REG-LABEL: SubRegIndex sub_odd:94// CHECK-REG: Offset: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }95// CHECK-REG: Size: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }96 97//============================================================================//98//--------------------- Encoding/Decoding parts ------------------------------//99//============================================================================//100def fooTypeEncDefault : InstructionEncoding {101 let Size = 8;102 field bits<64> SoftFail = 0;103 bits<64> Inst;104 bits<8> factor;105 let Inst{7...0} = factor;106 let Inst{3...2} = 0b10;107 let Inst{1...0} = 0b00;108}109 110def fooTypeEncA : InstructionEncoding {111 let Size = 4;112 field bits<32> SoftFail = 0;113 bits<32> Inst;114 bits<8> factor;115 let Inst{7...0} = factor;116 let Inst{3...2} = 0b11;117 let Inst{1...0} = 0b00;118}119 120 121def foo : Instruction {122 bits<32> Inst;123 let OutOperandList = (outs);124 let InOperandList = (ins i32imm:$factor);125 let EncodingInfos = EncodingByHwMode<126 [TestMode2, DefaultMode], [fooTypeEncA, fooTypeEncDefault]127 >;128 let AsmString = "foo $factor";129}130 131// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenMCSubtargetInfo::getHwModeSet() const {132// CHECK-SUBTARGET{LITERAL}:[[maybe_unused]] const FeatureBitset &FB = getFeatureBits();133// CHECK-SUBTARGET-NEXT: // Collect HwModes and store them as a bit set.134// CHECK-SUBTARGET-NEXT: unsigned Modes = 0;135// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1]) Modes |= (1 << 0);136// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat2]) Modes |= (1 << 1);137// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1] && FB[TestTarget::Feat2]) Modes |= (1 << 2);138// CHECK-SUBTARGET-NEXT: return Modes;139// CHECK-SUBTARGET-NEXT: }140 141// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwModeSet() const {142// CHECK-SUBTARGET{LITERAL}:[[maybe_unused]] const auto *Subtarget =143// CHECK-SUBTARGET-NEXT: static_cast<const TestTargetSubtarget *>(this);144// CHECK-SUBTARGET-NEXT: // Collect HwModes and store them as a bit set.145// CHECK-SUBTARGET-NEXT: unsigned Modes = 0;146// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat1())) Modes |= (1 << 0);147// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat2())) Modes |= (1 << 1);148// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat1()) && (Subtarget->hasFeat2())) Modes |= (1 << 2);149// CHECK-SUBTARGET-NEXT: return Modes;150// CHECK-SUBTARGET-NEXT: }151// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwMode(enum HwModeType type) const {152// CHECK-SUBTARGET: unsigned Modes = getHwModeSet();153// CHECK-SUBTARGET: if (!Modes)154// CHECK-SUBTARGET: return Modes;155// CHECK-SUBTARGET: switch (type) {156// CHECK-SUBTARGET: case HwMode_Default:157// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;158// CHECK-SUBTARGET: case HwMode_ValueType:159// CHECK-SUBTARGET: Modes &= 3;160// CHECK-SUBTARGET: if (!Modes)161// CHECK-SUBTARGET: return Modes;162// CHECK-SUBTARGET: if (!llvm::has_single_bit<unsigned>(Modes))163// CHECK-SUBTARGET: llvm_unreachable("Two or more HwModes for ValueType were found!");164// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;165// CHECK-SUBTARGET: case HwMode_RegInfo:166// CHECK-SUBTARGET: Modes &= 1;167// CHECK-SUBTARGET: if (!Modes)168// CHECK-SUBTARGET: return Modes;169// CHECK-SUBTARGET: if (!llvm::has_single_bit<unsigned>(Modes))170// CHECK-SUBTARGET: llvm_unreachable("Two or more HwModes for RegInfo were found!");171// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;172// CHECK-SUBTARGET: case HwMode_EncodingInfo:173// CHECK-SUBTARGET: Modes &= 4;174// CHECK-SUBTARGET: if (!Modes)175// CHECK-SUBTARGET: return Modes;176// CHECK-SUBTARGET: if (!llvm::has_single_bit<unsigned>(Modes))177// CHECK-SUBTARGET: llvm_unreachable("Two or more HwModes for EncodingInfo were found!");178// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;179// CHECK-SUBTARGET: }180// CHECK-SUBTARGET: llvm_unreachable("unexpected HwModeType");181// CHECK-SUBTARGET: return 0; // should not get here182// CHECK-SUBTARGET: }183