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1// RUN: llvm-tblgen %s | FileCheck %s2// XFAIL: vg_leak3 4class ValueType<int size, int value> {5 int Size = size;6 int Value = value;7}8 9def v2i64 : ValueType<128, 22>; // 2 x i64 vector value10def v2f64 : ValueType<128, 28>; // 2 x f64 vector value11 12class Intrinsic<string name> {13 string Name = name;14}15 16class Pattern<dag patternToMatch, list<dag> resultInstrs> {17 dag PatternToMatch = patternToMatch;18 list<dag> ResultInstrs = resultInstrs;19}20 21// Pat - A simple (but common) form of a pattern, which produces a simple result22// not needing a full list.23class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;24 25class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 26 list<dag> pattern> {27 bits<8> Opcode = opcode;28 dag OutOperands = oopnds;29 dag InOperands = iopnds;30 string AssemblyString = asmstr;31 list<dag> Pattern = pattern;32}33 34def ops;35def outs;36def ins;37 38def set;39 40// Define registers41class Register<string n> {42 string Name = n;43}44 45class RegisterClass<list<ValueType> regTypes, list<Register> regList> {46 list<ValueType> RegTypes = regTypes;47 list<Register> MemberList = regList;48}49 50def XMM0: Register<"xmm0">;51def XMM1: Register<"xmm1">;52def XMM2: Register<"xmm2">;53def XMM3: Register<"xmm3">;54def XMM4: Register<"xmm4">;55def XMM5: Register<"xmm5">;56def XMM6: Register<"xmm6">;57def XMM7: Register<"xmm7">;58def XMM8: Register<"xmm8">;59def XMM9: Register<"xmm9">;60def XMM10: Register<"xmm10">;61def XMM11: Register<"xmm11">;62def XMM12: Register<"xmm12">;63def XMM13: Register<"xmm13">;64def XMM14: Register<"xmm14">;65def XMM15: Register<"xmm15">;66 67def VR128 : RegisterClass<[v2i64, v2f64],68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,69 XMM8, XMM9, XMM10, XMM11,70 XMM12, XMM13, XMM14, XMM15]>;71 72// Dummy for subst73def REGCLASS : RegisterClass<[], []>;74def MNEMONIC;75 76// Define intrinsics77def int_x86_sse2_add_ps : Intrinsic<"addps">;78def int_x86_sse2_add_pd : Intrinsic<"addpd">;79def INTRINSIC : Intrinsic<"Dummy">;80def bitconvert;81 82class MakePat<list<dag> patterns> : Pat<patterns[0], patterns[1]>;83 84class Base<bits<8> opcode, dag opnds, dag iopnds, string asmstr, Intrinsic intr, 85 list<list<dag>> patterns>86 : Inst<opcode, opnds, iopnds, asmstr, 87 !foreach(pattern, patterns[0],88 !foreach(operand, pattern,89 !subst(INTRINSIC, intr, 90 !subst(REGCLASS, VR128, 91 !subst(MNEMONIC, set, operand)))))>,92 MakePat<!foreach(pattern, patterns[1],93 !foreach(operand, pattern,94 !subst(INTRINSIC, intr, 95 !subst(REGCLASS, VR128, 96 !subst(MNEMONIC, set, operand)))))>;97 98multiclass arith<bits<8> opcode, string asmstr, string intr, list<list<dag>> patterns> {99 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),100 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)), patterns>;101 102 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),103 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)), patterns>;104}105 106defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",107 // rr Patterns108 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],109 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),110 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]>;111 112// CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]113// CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]114