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1// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s2 3// Make sure we don't form ReadAdvances with ValidWrites entries that are not4// associated with any instructions.5 6include "llvm/Target/Target.td"7 8def TargetX : Target;9 10def WriteX : SchedWrite;11def WriteY : SchedWrite;12def ReadX : SchedRead;13 14def InstX : Instruction {15 let OutOperandList = (outs);16 let InOperandList = (ins);17 let SchedRW = [WriteX, ReadX];18}19 20def SchedModelX: SchedMachineModel {21 let CompleteModel = 0;22}23 24let SchedModel = SchedModelX in {25 def : ReadAdvance<ReadX, 1, [WriteX, WriteY]>;26 // CHECK: error: ReadAdvance referencing a ValidWrite that is not used by any instruction (WriteY)27}28 29def ProcessorX: ProcessorModel<"ProcessorX", SchedModelX, []>;30