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1// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s2 3include "llvm/Target/Target.td"4 5def MyTarget : Target;6 7def R0 : Register<"r0">;8def GR : RegisterClass<"MyTarget", [i32], 32, (add R0)>;9 10def F0 : Register<"f0">;11def FR : RegisterClass<"MyTarget", [f32], 32, (add F0)>;12 13def V0 : Register<"V0">;14def VR : RegisterClass<"MyTarget", [v4i8, f32], 32, (add V0)>;15 16def AllFloatR : RegisterClass<"MyTarget", [f32], 32, (add F0, V0)>;17def AnyR : RegisterClass<"MyTarget", [i32, f32, v4i8], 32, (add R0, F0, V0)>;18 19def GRRegBank : RegisterBank<"GRB", [GR]>;20def FRRegBank : RegisterBank<"FRB", [FR]>;21def VRRegBank : RegisterBank<"VRB", [VR]>;22 23 24// CHECK: #ifdef GET_TARGET_REGBANK_CLASS25// CHECK: const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;26 27// CHECK: #ifdef GET_TARGET_REGBANK_IMPL28// CHECK: const RegisterBank &29// CHECK-NEXT: MyTargetGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {30// CHECK-NEXT: constexpr uint32_t InvalidRegBankID = uint32_t(MyTarget::InvalidRegBankID) & 3;31// CHECK-NEXT: static const uint32_t RegClass2RegBank[1] = {32// CHECK-NEXT: (uint32_t(InvalidRegBankID) << 0) |33// CHECK-NEXT: (uint32_t(InvalidRegBankID) << 2) |34// CHECK-NEXT: (uint32_t(MyTarget::FRRegBankID) << 4) | // FRRegClassID35// CHECK-NEXT: (uint32_t(MyTarget::GRRegBankID) << 6) | // GRRegClassID36// CHECK-NEXT: (uint32_t(MyTarget::VRRegBankID) << 8) // VRRegClassID37// CHECK-NEXT: };38// CHECK-NEXT: const unsigned RegClassID = RC.getID();39// CHECK-NEXT: if (LLVM_LIKELY(RegClassID < 5)) {40// CHECK-NEXT: unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;41// CHECK-NEXT: if (RegBankID != InvalidRegBankID)42// CHECK-NEXT: return getRegBank(RegBankID);43// CHECK-NEXT: }44// CHECK-NEXT: llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());45// CHECK-NEXT: }46