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1// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s -o - | FileCheck -check-prefix=INSTRINFO %s2// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s -o - | FileCheck -check-prefix=ASMMATCHER %s3// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s -o - | FileCheck -check-prefix=DISASM %s4// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o - | FileCheck -check-prefix=ISEL-SDAG %s5// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o - | FileCheck -check-prefix=ISEL-GISEL %s6 7include "llvm/Target/Target.td"8 9// INSTRINFO: #ifdef GET_INSTRINFO_ENUM10// INSTRINFO-NEXT: #undef GET_INSTRINFO_ENUM11// INSTRINFO-EMPTY:12// INSTRINFO-NEXT: namespace llvm::MyTarget {13// INSTRINFO-EMPTY:14// INSTRINFO-NEXT: enum {15// INSTRINFO-NEXT: PHI16// INSTRINFO: LOAD_STACK_GUARD = [[LOAD_STACK_GUARD_OPCODE:[0-9]+]]17// INSTRINFO: };18// INSTRINFO: enum RegClassByHwModeUses : uint16_t {19// INSTRINFO-NEXT: MyPtrRC,20// INSTRINFO-NEXT: XRegs_EvenIfRequired,21// INSTRINFO-NEXT: YRegs_EvenIfRequired,22// INSTRINFO-NEXT: };23// INSTRINFO-EMPTY:24// INSTRINFO-NEXT: } // namespace llvm::MyTarget25 26 27// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_28 29// INSTRINFO: /* [[LOAD_STACK_GUARD_OP_INDEX]] */ { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },30// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },31// INSTRINFO: { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },32// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },33// INSTRINFO: { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },34 35// INSTRINFO: { MyTarget::XRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },36// INSTRINFO: { MyTarget::XRegs_EvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },37 38// INSTRINFO: { MyTarget::YRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },39 40// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { MyTarget::MyPtrRC, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },41// INSTRINFO: { MyTarget::YRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },42 43// INSTRINFO: extern const int16_t MyTargetRegClassByHwModeTables[4][3] = {44// INSTRINFO-NEXT: { // DefaultMode45// INSTRINFO-NEXT: MyTarget::PtrRegs32RegClassID,46// INSTRINFO-NEXT: MyTarget::XRegsRegClassID,47// INSTRINFO-NEXT: MyTarget::YRegsRegClassID,48// INSTRINFO-NEXT: },49// INSTRINFO-NEXT: { // EvenMode50// INSTRINFO-NEXT: -1, // Missing mode entry51// INSTRINFO-NEXT: MyTarget::XRegs_EvenRegClassID,52// INSTRINFO-NEXT: MyTarget::YRegs_EvenRegClassID,53// INSTRINFO-NEXT: },54// INSTRINFO-NEXT: { // OddMode55// INSTRINFO-NEXT: -1, // Missing mode entry56// INSTRINFO-NEXT: MyTarget::XRegs_OddRegClassID,57// INSTRINFO-NEXT: -1, // Missing mode entry58// INSTRINFO-NEXT: },59// INSTRINFO-NEXT: { // Ptr6460// INSTRINFO-NEXT: MyTarget::PtrRegs64RegClassID,61// INSTRINFO-NEXT: -1, // Missing mode entry62// INSTRINFO-NEXT: -1, // Missing mode entry63// INSTRINFO-NEXT: },64// INSTRINFO-NEXT: };65 66// INSTRINFO: static inline void InitMyTargetMCInstrInfo(67// INSTRINFO-NEXT: II->InitMCInstrInfo(MyTargetDescs.Insts, MyTargetInstrNameIndices, MyTargetInstrNameData, nullptr, nullptr, {{[0-9]+}}, &MyTargetRegClassByHwModeTables[0][0], 3);68 69 70 71// ASMMATCHER: enum MatchClassKind {72// ASMMATCHER: MCK_LAST_TOKEN = OptionalMatchClass,73// ASMMATCHER-NEXT: MCK_XRegs_Odd, // register class 'XRegs_Odd'74// ASMMATCHER-NEXT: MCK_PtrRegs32, // register class 'PtrRegs32'75// ASMMATCHER-NEXT: MCK_PtrRegs64, // register class 'PtrRegs64'76// ASMMATCHER-NEXT: MCK_XRegs_Even, // register class 'XRegs_Even'77// ASMMATCHER-NEXT: MCK_YRegs_Even, // register class 'YRegs_Even'78// ASMMATCHER-NEXT: MCK_XRegs, // register class 'XRegs'79// ASMMATCHER-NEXT: MCK_YRegs, // register class 'YRegs'80// ASMMATCHER-NEXT: MCK_LAST_REGISTER = MCK_YRegs,81// ASMMATCHER-NEXT: MCK_RegByHwMode_MyPtrRC, // register class by hwmode82// ASMMATCHER-NEXT: MCK_RegByHwMode_XRegs_EvenIfRequired, // register class by hwmode83// ASMMATCHER-NEXT: MCK_RegByHwMode_YRegs_EvenIfRequired, // register class by hwmode84// ASMMATCHER-NEXT: MCK_LAST_REGCLASS_BY_HWMODE = MCK_RegByHwMode_YRegs_EvenIfRequired,85// ASMMATCHER-NEXT: MCK_Imm, // user defined class 'ImmAsmOperand'86 87// ASMMATCHER: static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {88// ASMMATCHER: if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)89 90// ASMMATCHER: switch (Kind) {91 92// ASMMATCHER: if (Operand.isReg() && Kind > MCK_LAST_REGISTER && Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {93// ASMMATCHER-NEXT: static constexpr MatchClassKind RegClassByHwModeMatchTable[4][3] = {94// ASMMATCHER-NEXT: { // DefaultMode95// ASMMATCHER-NEXT: MCK_PtrRegs32,96// ASMMATCHER-NEXT: MCK_XRegs,97// ASMMATCHER-NEXT: MCK_YRegs,98// ASMMATCHER-NEXT: },99// ASMMATCHER-NEXT: { // EvenMode100// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode101// ASMMATCHER-NEXT: MCK_XRegs_Even,102// ASMMATCHER-NEXT: MCK_YRegs_Even,103// ASMMATCHER-NEXT: },104// ASMMATCHER-NEXT: { // OddMode105// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode106// ASMMATCHER-NEXT: MCK_XRegs_Odd,107// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode108// ASMMATCHER-NEXT: },109// ASMMATCHER-NEXT: { // Ptr64110// ASMMATCHER-NEXT: MCK_PtrRegs64,111// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode112// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode113// ASMMATCHER-NEXT: },114// ASMMATCHER-NEXT: };115// ASMMATCHER-EMPTY:116// ASMMATCHER-NEXT: static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == 3);117// ASMMATCHER-NEXT: const unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);118// ASMMATCHER-NEXT: Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER + 1)];119// ASMMATCHER-NEXT: }120 121// ASMMATCHER: if (Operand.isReg()) {122 123// ASMMATCHER: static const MatchEntry MatchTable0[] = {124// ASMMATCHER: /* also_my_load_1 */, MyTarget::MY_LOAD, Convert__RegByHwMode_XRegs_EvenIfRequired1_0__RegByHwMode_MyPtrRC1_1, AMFBS_None, { MCK_RegByHwMode_XRegs_EvenIfRequired, MCK_RegByHwMode_MyPtrRC }, },125// ASMMATCHER: /* also_my_load_2 */, MyTarget::MY_LOAD, Convert__RegByHwMode_XRegs_EvenIfRequired1_0__RegByHwMode_MyPtrRC1_1, AMFBS_None, { MCK_RegByHwMode_XRegs_EvenIfRequired, MCK_RegByHwMode_MyPtrRC }, },126// ASMMATCHER: /* always_all */, MyTarget::ALWAYS_ALL, Convert__Reg1_0, AMFBS_None, { MCK_XRegs }, },127// ASMMATCHER: /* always_even */, MyTarget::ALWAYS_EVEN, Convert__Reg1_0, AMFBS_None, { MCK_XRegs_Even }, },128// ASMMATCHER: /* custom_decode */, MyTarget::CUSTOM_DECODE, Convert__RegByHwMode_YRegs_EvenIfRequired1_0, AMFBS_None, { MCK_RegByHwMode_YRegs_EvenIfRequired }, },129// ASMMATCHER: /* even_if_mode */, MyTarget::EVEN_IF_MODE, Convert__RegByHwMode_XRegs_EvenIfRequired1_0, AMFBS_None, { MCK_RegByHwMode_XRegs_EvenIfRequired }, },130// ASMMATCHER: /* my_mov */, MyTarget::MY_MOV, Convert__RegByHwMode_YRegs_EvenIfRequired1_0__RegByHwMode_XRegs_EvenIfRequired1_1, AMFBS_None, { MCK_RegByHwMode_YRegs_EvenIfRequired, MCK_RegByHwMode_XRegs_EvenIfRequired }, },131 132 133 134// DISASM{LITERAL}: [[maybe_unused]]135// DISASM-NEXT: static DecodeStatus DecodeMyPtrRCRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {136// DISASM-NEXT: switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {137// DISASM-NEXT: case 0: // DefaultMode138// DISASM-NEXT: return DecodePtrRegs32RegisterClass(Inst, Imm, Addr, Decoder);139// DISASM-NEXT: case 3: // Ptr64140// DISASM-NEXT: return DecodePtrRegs64RegisterClass(Inst, Imm, Addr, Decoder);141// DISASM-NEXT: default:142// DISASM-NEXT: llvm_unreachable("no decoder for hwmode");143// DISASM-NEXT: }144// DISASM-NEXT: }145 146// DISASM{LITERAL}: [[maybe_unused]]147// DISASM-NEXT: static DecodeStatus DecodeXRegs_EvenIfRequiredRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {148// DISASM-NEXT: switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {149// DISASM-NEXT: case 0: // DefaultMode150// DISASM-NEXT: return DecodeXRegsRegisterClass(Inst, Imm, Addr, Decoder);151// DISASM-NEXT: case 1: // EvenMode152// DISASM-NEXT: return DecodeXRegs_EvenRegisterClass(Inst, Imm, Addr, Decoder);153// DISASM-NEXT: case 2: // OddMode154// DISASM-NEXT: return DecodeXRegs_OddRegisterClass(Inst, Imm, Addr, Decoder);155// DISASM-NEXT: default:156// DISASM-NEXT: llvm_unreachable("no decoder for hwmode");157// DISASM-NEXT: }158// DISASM-NEXT:}159// DISASM-EMPTY:160// DISASM{LITERAL}: [[maybe_unused]]161// DISASM-NEXT: static DecodeStatus DecodeYRegs_EvenIfRequiredRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {162// DISASM-NEXT: switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {163// DISASM-NEXT: case 0: // DefaultMode164// DISASM-NEXT: return DecodeYRegsRegisterClass(Inst, Imm, Addr, Decoder);165// DISASM-NEXT: case 1: // EvenMode166// DISASM-NEXT: return DecodeYRegs_EvenRegisterClass(Inst, Imm, Addr, Decoder);167// DISASM-NEXT: default:168// DISASM-NEXT: llvm_unreachable("no decoder for hwmode");169// DISASM-NEXT: }170// DISASM-NEXT:}171 172// DISASM: static DecodeStatus decodeToMCInst(173// DISASM: switch (Idx) {174// DISASM: case 0:175// DISASM: if (!Check(S, DecodeYRegs_EvenIfRequiredRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }176// DISASM: if (!Check(S, DecodeXRegs_EvenIfRequiredRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }177 178// DISASM: case 1:179// DISASM: if (!Check(S, DecodeXRegs_EvenIfRequiredRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }180 181// DISASM: case 2:182// DISASM: if (!Check(S, DecodeXRegs_EvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }183// DISASM: case 3:184// DISASM: if (!Check(S, DecodeXRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }185 186// DISASM: case 4:187// DISASM: if (!Check(S, YEvenIfRequiredCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }188 189 190// ISEL-SDAG: MatcherTable191// ISEL-SDAG: OPC_SwitchOpcode /*2 cases */, {{[0-9]+}}, TARGET_VAL(ISD::STORE),192// ISEL-SDAG: OPC_RecordMemRef,193// ISEL-SDAG: OPC_RecordNode, // #0 = 'st' chained node194// ISEL-SDAG: OPC_RecordChild1, // #1 = $val195// ISEL-SDAG-NEXT: OPC_RecordChild2, // #2 = $src196// ISEL-SDAG-NEXT: OPC_CheckChild2TypeI64,197// ISEL-SDAG-NEXT: OPC_CheckPredicate2, // Predicate_unindexedstore198// ISEL-SDAG-NEXT: OPC_CheckPredicate3, // Predicate_store199// ISEL-SDAG: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs,200 201// ISEL-SDAG: /*SwitchOpcode*/ {{[0-9]+}}, TARGET_VAL(ISD::LOAD),202// ISEL-SDAG-NEXT: OPC_RecordMemRef,203// ISEL-SDAG-NEXT: OPC_RecordNode, // #0 = 'ld' chained node204// ISEL-SDAG-NEXT: OPC_RecordChild1, // #1 = $src205// ISEL-SDAG-NEXT: OPC_CheckTypeI64,206// ISEL-SDAG-NEXT: OPC_Scope, {{[0-9]+}}, /*->{{[0-9]+}}*/ // 2 children in Scope207// ISEL-SDAG-NEXT: OPC_CheckChild1TypeI32,208// ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedload209// ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_load210// ISEL-SDAG-NEXT: OPC_Scope, {{[0-9]+}}, /*->{{[0-9]+}}*/ // 3 children in Scope211// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate1, // (Subtarget->hasAlignedRegisters())212// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,213// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,214 215// ISEL-SDAG: /*Scope*/216// ISEL-SDAG: OPC_CheckPatternPredicate2, // (Subtarget->hasUnalignedRegisters())217// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,218// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,219 220// ISEL-SDAG: /*Scope*/221// ISEL-SDAG: OPC_CheckPatternPredicate3, // !((Subtarget->hasAlignedRegisters())) && !((Subtarget->hasUnalignedRegisters())) && !((Subtarget->isPtr64()))222// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,223// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,224 225// ISEL-SDAG: /*Scope*/226// ISEL-SDAG-NEXT: OPC_CheckChild1TypeI64,227// ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedload228// ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_load229// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate0, // (Subtarget->isPtr64())230// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,231// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,232 233 234 235 236 237// ISEL-GISEL: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(148),238// ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,239// ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,240// ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,241// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),242// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(101),243// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,244 245// FIXME: This should be a direct check for regbank, not have an incorrect class246 247// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),248// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(85), // Rule ID 1 //249// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),250// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)251// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),252// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,253// ISEL-GISEL-NEXT: // GIR_Coverage, 1,254// ISEL-GISEL-NEXT: GIR_Done,255// ISEL-GISEL-NEXT: // Label 5: @85256// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(100), // Rule ID 2 //257// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),258// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)259// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),260// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,261// ISEL-GISEL-NEXT: // GIR_Coverage, 2,262// ISEL-GISEL-NEXT: GIR_Done,263// ISEL-GISEL-NEXT: // Label 6: @100264// ISEL-GISEL-NEXT: GIM_Reject,265// ISEL-GISEL-NEXT: // Label 4: @101266// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(124), // Rule ID 3 //267// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),268// ISEL-GISEL-NEXT: // MIs[0] src269// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,270// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),271// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i64] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i64] }:$src)272// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),273// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,274// ISEL-GISEL-NEXT: // GIR_Coverage, 3,275// ISEL-GISEL-NEXT: GIR_Done,276// ISEL-GISEL-NEXT: // Label 7: @124277// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(147), // Rule ID 4 //278// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),279// ISEL-GISEL-NEXT: // MIs[0] src280// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,281// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),282// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)283// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),284// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,285// ISEL-GISEL-NEXT: // GIR_Coverage, 4,286// ISEL-GISEL-NEXT: GIR_Done,287// ISEL-GISEL-NEXT: // Label 8: @147288// ISEL-GISEL-NEXT: GIM_Reject,289// ISEL-GISEL-NEXT: // Label 3: @148290// ISEL-GISEL-NEXT: GIM_Reject,291// ISEL-GISEL-NEXT: // Label 1: @149292// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(186), // Rule ID 0 //293// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),294// ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,295// ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,296// ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,297// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),298// ISEL-GISEL-NEXT: // MIs[0] src299// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,300// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),301// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, XRegs_EvenIfRequired:{ *:[i64] }:$src)302// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),303// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,304 305 306 307def HasAlignedRegisters : Predicate<"Subtarget->hasAlignedRegisters()">;308def HasUnalignedRegisters : Predicate<"Subtarget->hasUnalignedRegisters()">;309def IsPtr64 : Predicate<"Subtarget->isPtr64()">;310 311// FIXME: In reality these should be mutually exclusive and we need312// the cross product of even mode / ptr size. i.e. EvenModePtr64,313// OddMode32 etc. For the purposes of this test where we won't be314// executing the code to compute a mode ID, it's simpler to pretend315// these are orthogonal.316def EvenMode : HwMode<[HasAlignedRegisters]>;317def OddMode : HwMode<[HasUnalignedRegisters]>;318def Ptr64 : HwMode<[IsPtr64]>;319 320class MyReg<string n>321 : Register<n> {322 let Namespace = "MyTarget";323}324 325class MyClass<int size, list<ValueType> types, dag registers>326 : RegisterClass<"MyTarget", types, size, registers> {327 let Size = size;328}329 330def X0 : MyReg<"x0">;331def X1 : MyReg<"x1">;332def X2 : MyReg<"x2">;333def X3 : MyReg<"x3">;334def X4 : MyReg<"x4">;335def X5 : MyReg<"x5">;336def X6 : MyReg<"x6">;337 338def Y0 : MyReg<"y0">;339def Y1 : MyReg<"y1">;340def Y2 : MyReg<"y2">;341def Y3 : MyReg<"y3">;342def Y4 : MyReg<"y4">;343def Y5 : MyReg<"y5">;344def Y6 : MyReg<"y6">;345 346 347 348def P0_32 : MyReg<"p0">;349def P1_32 : MyReg<"p1">;350def P2_32 : MyReg<"p2">;351def P3_32 : MyReg<"p3">;352 353def P0_64 : MyReg<"p0_64">;354def P1_64 : MyReg<"p1_64">;355def P2_64 : MyReg<"p2_64">;356def P3_64 : MyReg<"p3_64">;357 358 359 360def XRegs : RegisterClass<"MyTarget", [i64], 64, (add X0, X1, X2, X3, X4, X5, X6)>;361def XRegs_Odd : RegisterClass<"MyTarget", [i64], 64, (add X1, X3, X5)>;362def XRegs_Even : RegisterClass<"MyTarget", [i64], 64, (add X0, X2, X4, X6)>;363 364def XRegs_EvenIfRequired : RegClassByHwMode<[DefaultMode, EvenMode, OddMode],365 [XRegs, XRegs_Even, XRegs_Odd]>;366 367def YRegs : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y1, Y2, Y3, Y4, Y5, Y6)>;368def YRegs_Even : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y2, Y4, Y6)>;369 370def YRegs_EvenIfRequired : RegClassByHwMode<[DefaultMode, EvenMode],371 [YRegs, YRegs_Even]>;372 373 374def PtrRegs32 : RegisterClass<"MyTarget", [i32], 32, (add P0_32, P1_32, P2_32, P3_32)>;375def PtrRegs64 : RegisterClass<"MyTarget", [i64], 64, (add P0_64, P1_64, P2_64, P3_64)>;376 377def MyPtrRC : RegClassByHwMode<[DefaultMode, Ptr64],378 [PtrRegs32, PtrRegs64]>;379 380 381def PtrRegOperand : RegisterOperand<MyPtrRC>;382 383 384def CustomDecodeYEvenIfRequired : RegisterOperand<YRegs_EvenIfRequired> {385 let DecoderMethod = "YEvenIfRequiredCustomDecoder";386}387 388class TestInstruction : Instruction {389 let Size = 2;390 let Namespace = "MyTarget";391 let hasSideEffects = false;392 let hasExtraSrcRegAllocReq = false;393 let hasExtraDefRegAllocReq = false;394 395 field bits<16> Inst;396 bits<3> dst;397 bits<3> src;398 bits<3> opcode;399 400 let Inst{2-0} = dst;401 let Inst{5-3} = src;402 let Inst{7-5} = opcode;403}404 405def SpecialOperand : RegisterOperand<XRegs_EvenIfRequired>;406 407def MY_MOV : TestInstruction {408 let OutOperandList = (outs YRegs_EvenIfRequired:$dst);409 let InOperandList = (ins XRegs_EvenIfRequired:$src);410 let AsmString = "my_mov $dst, $src";411 let opcode = 0;412}413 414def EVEN_IF_MODE : TestInstruction {415 let OutOperandList = (outs);416 let InOperandList = (ins XRegs_EvenIfRequired:$src);417 let AsmString = "even_if_mode $src";418 let opcode = 1;419}420 421def ALWAYS_EVEN : TestInstruction {422 let OutOperandList = (outs);423 let InOperandList = (ins XRegs_Even:$src);424 let AsmString = "always_even $src";425 let opcode = 2;426}427 428def ALWAYS_ALL : TestInstruction {429 let OutOperandList = (outs);430 let InOperandList = (ins XRegs:$src);431 let AsmString = "always_all $src";432 let opcode = 3;433}434 435def CUSTOM_DECODE : TestInstruction {436 let OutOperandList = (outs);437 let InOperandList = (ins CustomDecodeYEvenIfRequired:$src);438 let AsmString = "custom_decode $src";439 let opcode = 4;440}441 442def MyTargetMov : SDNode<"MyTarget::MY_MOV", SDTUnaryOp, []>;443 444// Test 2 different cases directly in the instruction445def MY_STORE : TestInstruction {446 let OutOperandList = (outs);447 let InOperandList = (ins XRegs_EvenIfRequired:$src, MyPtrRC:$dst);448 let AsmString = "my_store $src, $dst";449 let opcode = 5;450}451 452// Test 2 different cases wrapped by RegisterOperand453def MY_LOAD : TestInstruction {454 let OutOperandList = (outs RegisterOperand<XRegs_EvenIfRequired>:$dst);455 let InOperandList = (ins PtrRegOperand:$src);456 let AsmString = "my_load $dst, $src";457 let opcode = 6;458}459 460// Direct RegClassByHwMode reference461def MY_LOAD_ALIAS1 : InstAlias<"also_my_load_1 $dst, $src",462 (MY_LOAD XRegs_EvenIfRequired:$dst, MyPtrRC:$src)>;463 464// RegClassByHwMode wrapped in RegisterOperand465def MY_LOAD_ALIAS2 : InstAlias<"also_my_load_2 $dst, $src",466 (MY_LOAD RegisterOperand<XRegs_EvenIfRequired>:$dst, PtrRegOperand:$src)>;467 468// Direct RegClassByHwMode usage469def : Pat<470 (store XRegs_EvenIfRequired:$val, MyPtrRC:$src),471 (MY_STORE $val, XRegs_EvenIfRequired:$src)472>;473 474// Wrapped in RegisterOperand475def : Pat<476 (i64 (load PtrRegOperand:$src)),477 (MY_LOAD $src)478>;479 480defm : RemapAllTargetPseudoPointerOperands<XRegs_EvenIfRequired>;481 482def MyTargetISA : InstrInfo;483def MyTarget : Target { let InstructionSet = MyTargetISA; }484