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1// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s2 3// Check that EncoderMethod for RegisterOperand is working correctly4 5include "llvm/Target/Target.td"6 7def ArchInstrInfo : InstrInfo { }8 9def Arch : Target {10 let InstructionSet = ArchInstrInfo;11}12 13def Reg : Register<"reg">;14 15def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;16 17def RegOperand : RegisterOperand<RegClass> {18 let EncoderMethod = "barEncoder";19}20 21def foo1 : Instruction {22 let Size = 1;23 24 let OutOperandList = (outs);25 let InOperandList = (ins RegOperand:$bar);26 27 bits<8> bar;28 bits<8> Inst = bar;29}30 31// CHECK: case ::foo1: {32// CHECK: op = barEncoder33// CHECK: Value |= (op & 0xff);34// CHECK: break;35// CHECK: }36 37 38// Also check that it works from a complex operand.39 40def RegPair : Operand<i32> {41 let MIOperandInfo = (ops RegOperand, RegOperand);42}43 44def foo2 : Instruction {45 let Size = 1;46 47 let OutOperandList = (outs);48 let InOperandList = (ins (RegPair $r1, $r2):$r12);49 50 bits<4> r1;51 bits<4> r2;52 bits<8> Inst;53 let Inst{3-0} = r1;54 let Inst{7-4} = r2;55}56 57// CHECK: case ::foo2: {58// CHECK: op = barEncoder59// CHECK: Value |= (op & 0xf);60// CHECK: op = barEncoder61// CHECK: Value |= (op & 0xf) << 4;62// CHECK: break;63// CHECK: }64