brintos

brintos / llvm-project-archived public Read only

0
0
Text · 1.4 KiB · 1249450 Raw
41 lines · plain
1// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s2 3include "llvm/Target/Target.td"4 5let Namespace = "MyTarget" in {6  def R0 : Register<"r0">; // base class BaseA7  def R1 : Register<"r1">; // base class BaseA8  def R2 : Register<"r2">; // base class BaseC9  def R3 : Register<"r3">; // base class BaseC10  def R4 : Register<"r4">; // base class BaseB11  def R5 : Register<"r5">; // base class BaseB12  def R6 : Register<"r6">; // no base class13} // Namespace = "MyTarget"14 15 16// BaseA and BaseB are equal ordered so enumeration order determines base class for overlaps17def BaseA : RegisterClass<"MyTarget", [i32], 32, (sequence "R%u", 0, 3)> {18  let BaseClassOrder = 1;19}20def BaseB : RegisterClass<"MyTarget", [i32], 32, (sequence "R%u", 3, 5)> {21  let BaseClassOrder = 1;22}23 24// BaseC defined order overrides BaseA and BaseB25def BaseC : RegisterClass<"MyTarget", [i32], 32, (sequence "R%u", 2, 3)> {26  let BaseClassOrder = 0;27}28 29def MyTarget : Target;30 31// CHECK:      static const uint16_t Mapping[8] = {32// CHECK-NEXT:   InvalidRegClassID,  // NoRegister33// CHECK-NEXT:   MyTarget::BaseARegClassID,  // R034// CHECK-NEXT:   MyTarget::BaseARegClassID,  // R135// CHECK-NEXT:   MyTarget::BaseCRegClassID,  // R236// CHECK-NEXT:   MyTarget::BaseCRegClassID,  // R337// CHECK-NEXT:   MyTarget::BaseBRegClassID,  // R438// CHECK-NEXT:   MyTarget::BaseBRegClassID,  // R539// CHECK-NEXT:   InvalidRegClassID,  // R640// CHECK-NEXT: };41