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1// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s2 3// Check if VarLenCodeEmitterGen works correctly.4 5include "llvm/Target/Target.td"6 7def ArchInstrInfo : InstrInfo { }8 9def Arch : Target {10 let InstructionSet = ArchInstrInfo;11}12 13def Reg : Register<"reg">;14 15def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;16 17def GR64 : RegisterOperand<RegClass>;18 19class MyMemOperand<dag sub_ops> : Operand<iPTR> {20 let MIOperandInfo = sub_ops;21 dag Base;22 dag Extension;23}24 25class MyVarInst<MyMemOperand memory_op> : Instruction {26 dag Inst;27 28 let OutOperandList = (outs GR64:$dst);29 let InOperandList = (ins memory_op:$src);30 31 // Testing `ascend` and `descend`32 let Inst = (ascend33 (descend 0b10110111, memory_op.Base),34 memory_op.Extension,35 // Testing operand referencing.36 (operand "$dst", 4),37 // Testing operand referencing with a certain bit range.38 (slice "$dst", 3, 1),39 // Testing slice hi/lo swap.40 (slice "$dst", 1, 3),41 // Testing custom encoder42 (operand "$dst", 2, (encoder "myCustomEncoder"))43 );44}45 46class MemOp16<string op_name> : MyMemOperand<(ops GR64:$reg, i16imm:$offset)> {47 // Testing sub-operand referencing.48 let Base = (operand "$"#op_name#".reg", 8);49 let Extension = (operand "$"#op_name#".offset", 16);50}51 52class MemOp32<string op_name> : MyMemOperand<(ops GR64:$reg, i32imm:$offset)> {53 let Base = (operand "$"#op_name#".reg", 8);54 // Testing variable-length instruction encoding.55 let Extension = (operand "$"#op_name#".offset", 32);56}57 58def FOO16 : MyVarInst<MemOp16<"src">>;59def FOO32 : MyVarInst<MemOp32<"src">>;60 61// The fixed bits part62// CHECK: {/*NumBits*/44,63// CHECK-SAME: // FOO1664// CHECK: {/*NumBits*/60,65// CHECK-SAME: // FOO3266// CHECK: UINT64_C(46848), // FOO1667// CHECK: UINT64_C(46848), // FOO3268 69// CHECK-LABEL: case ::FOO16: {70// CHECK: Scratch.getBitWidth() < 1671// src.reg72// CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);73// CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);74// src.offset75// CHECK: getMachineOpValue(MI, MI.getOperand(2), /*Pos=*/16, Scratch, Fixups, STI);76// CHECK: Inst.insertBits(Scratch.extractBits(16, 0), 16);77// 1st dst78// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/32, Scratch, Fixups, STI);79// CHECK: Inst.insertBits(Scratch.extractBits(4, 0), 32);80// 2nd dst81// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/36, Scratch, Fixups, STI);82// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 36);83// Slice hi/lo swap84// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/39, Scratch, Fixups, STI);85// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 39);86// dst w/ custom encoder87// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/42, Scratch, Fixups, STI);88// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 42);89 90// CHECK-LABEL: case ::FOO32: {91// CHECK: Scratch.getBitWidth() < 3292// src.reg93// CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);94// CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);95// src.offset96// CHECK: getMachineOpValue(MI, MI.getOperand(2), /*Pos=*/16, Scratch, Fixups, STI);97// CHECK: Inst.insertBits(Scratch.extractBits(32, 0), 16);98// 1st dst99// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/48, Scratch, Fixups, STI);100// CHECK: Inst.insertBits(Scratch.extractBits(4, 0), 48);101// 2nd dst102// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/52, Scratch, Fixups, STI);103// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 52);104// Slice hi/lo swap105// CHECK: getMachineOpValue(MI, MI.getOperand(0), /*Pos=*/55, Scratch, Fixups, STI);106// CHECK: Inst.insertBits(Scratch.extractBits(3, 1), 55);107// dst w/ custom encoder108// CHECK: myCustomEncoder(MI, /*OpIdx=*/0, /*Pos=*/58, Scratch, Fixups, STI);109// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 58);110