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1// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s2//3// CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Test::subreg_hh32 or Test::subreg_h324// CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::subreg_ll32 or Test::subreg_l325 6include "llvm/Target/Target.td"7 8def TestInstrInfo : InstrInfo {9}10 11def Test : Target {12 let InstructionSet = TestInstrInfo;13}14 15let Namespace = "Test" in {16 def subreg_l32 : SubRegIndex<32, 0>;17 def subreg_h32 : SubRegIndex<32, 32>;18 def subreg_h64 : SubRegIndex<64, 64>;19 def subreg_l64 : SubRegIndex<64, 0>;20 def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>;21 def subreg_ll32 : ComposedSubRegIndex<subreg_l64, subreg_l32>;22}23 24class TestReg<string n, list<Register> s> : RegisterWithSubRegs<n, s> {25 let Namespace = "Test";26}27 28// --------------------------------------------------------------------29// A situation that previously caused the warning about ambiguous30// composition.31//32// The actual subregister actions are:33// subreg_h64: { F0Q->F0D V0Q->F0D }34// subreg_h32: { F0D->F0S F0Q->F2S V0Q->F0S }35// composition: { F0Q->F0S V0Q->F0S } (this is the same as subreg_hh32)36// 37// For the register V0Q, subreg_hh32(V0Q) = subreg_h32(V0Q) = F0S, which38// would be enough to trigger the warning about ambiguous composition.39// However, for F0Q, subreg_hh32(F0Q) = F0S, while subreg_h32(F0Q) = F2S,40// which shows that there two subregister indices are different.41// Make sure that the warning is not emitted in this case.42 43class FPR32<string n> : TestReg<n, []> {44}45 46class FPR64<string n, FPR32 high> : TestReg<n, [high]> {47 let SubRegIndices = [subreg_h32];48}49 50class FPR128<string n, FPR64 high, FPR32 low> : TestReg<n, [high, low]> {51 let SubRegIndices = [subreg_h64, subreg_h32];52}53 54class VPR128<string n, FPR64 high> : TestReg<n, [high]> {55 let SubRegIndices = [subreg_h64];56}57 58def F0S : FPR32<"f0s">;59def F1S : FPR32<"f1s">;60def F2S : FPR32<"f2s">;61 62def F0D : FPR64<"f0d", F0S>;63def F0Q : FPR128<"f0q", F0D, F2S>;64def V0Q : VPR128<"v0q", F0D>;65 66def FP32 : RegisterClass<"FP32", [f32], 32, (add F0S)>;67def FP64 : RegisterClass<"FP64", [f64], 64, (add F0D)>;68def FP128 : RegisterClass<"FP128", [v2f64], 128, (add F0Q)>;69def VP128 : RegisterClass<"VP128", [v2f64], 128, (add V0Q)>;70 71// --------------------------------------------------------------------72// A situation where the warning is legitimate.73// Make sure that the warning is still displayed.74 75class GPR32<string n> : TestReg<n, []> {76}77 78class GPR64<string n, GPR32 low> : TestReg<n, [low]> {79 let SubRegIndices = [subreg_l32];80}81 82class GPR128<string n, GPR64 low> : TestReg<n, [low]> {83 let SubRegIndices = [subreg_l64];84}85 86def G0S : GPR32<"g0s">;87def G0D : GPR64<"g0d", G0S>;88def G0Q : GPR128<"g0q", G0D>;89 90def GP32 : RegisterClass<"GP32", [i32], 32, (add G0S)>;91def GP64 : RegisterClass<"GP64", [i64], 64, (add G0D)>;92def GP128 : RegisterClass<"GP128", [v2i64], 128, (add G0Q)>;93