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1// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s2 3// Test to check the bare minimum pressure sets.4// At least one register pressure set is required for the target.5// Allowed the pset only for D_32 regclass and ignored it for all6// other classes including the tuples.7include "llvm/Target/Target.td"8 9class MyClass<int size, list<ValueType> types, dag registers>10 : RegisterClass<"MyTarget", types, size, registers> {11 let Size = size;12}13 14def sub0 : SubRegIndex<32>;15def sub1 : SubRegIndex<32, 32>;16 17let Namespace = "MyTarget" in {18 def D : Register<"d">;19 foreach Index = 0-7 in {20 def S#Index : Register <"s"#Index>;21 }22}23 24// Should generate psets for D_3225def D_32 : MyClass<32, [i32], (add D)>;26 27let GeneratePressureSet = 0 in {28 def S_32 : MyClass<32, [i32], (sequence "S%u", 0, 7)>;29 def SD_32 : MyClass<32, [i32], (add S_32, D_32)>;30}31 32def S_64 : RegisterTuples<[sub0, sub1],33 [(decimate (shl S_32, 0), 1),34 (decimate (shl S_32, 1), 1)35 ]>;36 37def SReg_64 : MyClass<64, [i64], (add S_64)> {38 let GeneratePressureSet = 0;39}40 41def MyTarget : Target;42 43// CHECK-LABEL: // Register pressure sets enum.44// CHECK-NEXT: namespace MyTarget {45// CHECK-NEXT: enum RegisterPressureSets {46// CHECK-NEXT: D_32 = 0,47// CHECK-NEXT: };48// NAMESPACE-NEXT: } // end namespace TestNamespace49 50// CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {51// CHECK-NEXT: static const char *PressureNameTable[] = {52// CHECK-NEXT: "D_32",53// CHECK-NEXT: };54// CHECK-NEXT: return PressureNameTable[Idx];55// CHECK-NEXT: }56 57// CHECK: unsigned MyTargetGenRegisterInfo::58// CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {59// CHECK-NEXT: static const uint8_t PressureLimitTable[] = {60// CHECK-NEXT: {{[0-9]+}}, // 0: D_3261// CHECK-NEXT: };62// CHECK-NEXT: return PressureLimitTable[Idx];63// CHECK-NEXT:}64 65// CHECK: static const int RCSetsTable[] = {66// CHECK-NEXT: /* 0 */ 0, -1,67// CHECK-NEXT: };68