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1// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s2 3include "llvm/Target/Target.td"4 5def archInstrInfo : InstrInfo {}6 7def arch : Target {8 let InstructionSet = archInstrInfo;9}10 11def R0 : Register<"r0">;12def P0 : Register<"p0">;13def R32 : RegisterClass<"MyNS", [i32], 0, (add R0)>;14def P1 : RegisterClass<"MyNS", [i1], 0, (add P0)>;15 16def Reg3Opnd : Operand<OtherVT> {17 let MIOperandInfo = (ops R32, R32, P1);18}19 20// The following checks verify that 'MCInstrDesc' entry for 'InstA' has the21// expected 'NumOperands' and 'NumDefs', i.e. 'InstA' should have 3 defs out of22// 4 operands.23 24// CHECK: archInstrTable {{.* = \{}}25// CHECK: {{\{}}26// CHECK: {{\{}} [[ID:[0-9]+]], 4, 3, 13, {{.+\}, \/\/}}27// CHECK-SAME: InstA28def InstA : Instruction {29 let Namespace = "MyNS";30 let Size = 13;31 // InstA should have 3 defs out of 4 operands.32 let OutOperandList = (outs Reg3Opnd:$dst);33 let InOperandList = (ins i32imm:$c);34 field bits<8> Inst;35 field bits<8> SoftFail = 0;36 let hasSideEffects = false;37}38 39defm : RemapAllTargetPseudoPointerOperands<P1>;40