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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes=sroa,instcombine,aggressive-instcombine %s -S -o - | FileCheck %s3 4define i64 @quux(ptr %arg) {5; CHECK-LABEL: define i64 @quux(6; CHECK-SAME: ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[BB:.*:]]8; CHECK-NEXT: [[LOAD:%.*]] = load i64, ptr [[ARG]], align 19; CHECK-NEXT: ret i64 [[LOAD]]10;11bb:12 %load = load i8, ptr %arg, align 113 %getelementptr = getelementptr inbounds nuw i8, ptr %arg, i64 114 %load1 = load i8, ptr %getelementptr, align 115 %getelementptr2 = getelementptr inbounds nuw i8, ptr %arg, i64 216 %load3 = load i8, ptr %getelementptr2, align 117 %getelementptr4 = getelementptr inbounds nuw i8, ptr %arg, i64 318 %load5 = load i8, ptr %getelementptr4, align 119 %getelementptr6 = getelementptr inbounds nuw i8, ptr %arg, i64 420 %load7 = load i8, ptr %getelementptr6, align 121 %getelementptr8 = getelementptr inbounds nuw i8, ptr %arg, i64 522 %load9 = load i8, ptr %getelementptr8, align 123 %getelementptr10 = getelementptr inbounds nuw i8, ptr %arg, i64 624 %load11 = load i8, ptr %getelementptr10, align 125 %getelementptr12 = getelementptr inbounds nuw i8, ptr %arg, i64 726 %load13 = load i8, ptr %getelementptr12, align 127 %zext = zext i8 %load13 to i6428 %shl = shl nuw i64 %zext, 5629 %zext14 = zext i8 %load11 to i6430 %shl15 = shl nuw nsw i64 %zext14, 4831 %or = or disjoint i64 %shl, %shl1532 %zext16 = zext i8 %load9 to i6433 %shl17 = shl nuw nsw i64 %zext16, 4034 %or18 = or disjoint i64 %or, %shl1735 %zext19 = zext i8 %load7 to i6436 %shl20 = shl nuw nsw i64 %zext19, 3237 %or21 = or disjoint i64 %or18, %shl2038 %zext22 = zext i8 %load5 to i6439 %shl23 = shl nuw nsw i64 %zext22, 2440 %or24 = or disjoint i64 %or21, %shl2341 %zext25 = zext i8 %load3 to i6442 %shl26 = shl nuw nsw i64 %zext25, 1643 %zext27 = zext i8 %load1 to i6444 %shl28 = shl nuw nsw i64 %zext27, 845 %or29 = or disjoint i64 %or24, %shl2646 %zext30 = zext i8 %load to i6447 %or31 = or i64 %or29, %shl2848 %or32 = or i64 %or31, %zext3049 ret i64 %or3250}51 52 53; The following test case reduced from a client kernel54define fastcc <16 x float> @hoge(ptr %arg) {55; CHECK-LABEL: define fastcc <16 x float> @hoge(56; CHECK-SAME: ptr [[ARG:%.*]]) #[[ATTR0]] {57; CHECK-NEXT: [[BB:.*:]]58; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr [[ARG]], align 859; CHECK-NEXT: [[LOAD28:%.*]] = load i64, ptr [[LOAD]], align 160; CHECK-NEXT: [[GETELEMENTPTR72:%.*]] = getelementptr i8, ptr [[LOAD]], i64 861; CHECK-NEXT: [[LOAD73:%.*]] = load i64, ptr [[GETELEMENTPTR72]], align 162; CHECK-NEXT: [[GETELEMENTPTR120:%.*]] = getelementptr i8, ptr [[LOAD]], i64 1663; CHECK-NEXT: [[LOAD121:%.*]] = load i64, ptr [[GETELEMENTPTR120]], align 164; CHECK-NEXT: [[GETELEMENTPTR168:%.*]] = getelementptr i8, ptr [[LOAD]], i64 2465; CHECK-NEXT: [[LOAD169:%.*]] = load i64, ptr [[GETELEMENTPTR168]], align 166; CHECK-NEXT: [[CALL:%.*]] = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 [[LOAD28]], i64 0, <16 x float> zeroinitializer, i32 0, i32 0, i32 0)67; CHECK-NEXT: [[CALL225:%.*]] = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 [[LOAD73]], i64 0, <16 x float> [[CALL]], i32 0, i32 0, i32 0)68; CHECK-NEXT: [[CALL230:%.*]] = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 [[LOAD121]], i64 0, <16 x float> [[CALL225]], i32 0, i32 0, i32 0)69; CHECK-NEXT: [[CALL235:%.*]] = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 [[LOAD169]], i64 0, <16 x float> [[CALL230]], i32 0, i32 0, i32 0)70; CHECK-NEXT: ret <16 x float> [[CALL235]]71;72bb:73 %load = load ptr, ptr %arg, align 874 %load28 = load i8, ptr %load, align 175 %getelementptr30 = getelementptr i8, ptr %load, i64 176 %load31 = load i8, ptr %getelementptr30, align 177 %getelementptr36 = getelementptr i8, ptr %load, i64 278 %load37 = load i8, ptr %getelementptr36, align 179 %getelementptr42 = getelementptr i8, ptr %load, i64 380 %load43 = load i8, ptr %getelementptr42, align 181 %getelementptr48 = getelementptr i8, ptr %load, i64 482 %load49 = load i8, ptr %getelementptr48, align 183 %getelementptr54 = getelementptr i8, ptr %load, i64 584 %load55 = load i8, ptr %getelementptr54, align 185 %getelementptr60 = getelementptr i8, ptr %load, i64 686 %load61 = load i8, ptr %getelementptr60, align 187 %getelementptr66 = getelementptr i8, ptr %load, i64 788 %load67 = load i8, ptr %getelementptr66, align 189 %getelementptr72 = getelementptr i8, ptr %load, i64 890 %load73 = load i8, ptr %getelementptr72, align 191 %getelementptr78 = getelementptr i8, ptr %load, i64 992 %load79 = load i8, ptr %getelementptr78, align 193 %getelementptr84 = getelementptr i8, ptr %load, i64 1094 %load85 = load i8, ptr %getelementptr84, align 195 %getelementptr90 = getelementptr i8, ptr %load, i64 1196 %load91 = load i8, ptr %getelementptr90, align 197 %getelementptr96 = getelementptr i8, ptr %load, i64 1298 %load97 = load i8, ptr %getelementptr96, align 199 %getelementptr102 = getelementptr i8, ptr %load, i64 13100 %load103 = load i8, ptr %getelementptr102, align 1101 %getelementptr108 = getelementptr i8, ptr %load, i64 14102 %load109 = load i8, ptr %getelementptr108, align 1103 %getelementptr114 = getelementptr i8, ptr %load, i64 15104 %load115 = load i8, ptr %getelementptr114, align 1105 %getelementptr120 = getelementptr i8, ptr %load, i64 16106 %load121 = load i8, ptr %getelementptr120, align 1107 %getelementptr126 = getelementptr i8, ptr %load, i64 17108 %load127 = load i8, ptr %getelementptr126, align 1109 %getelementptr132 = getelementptr i8, ptr %load, i64 18110 %load133 = load i8, ptr %getelementptr132, align 1111 %getelementptr138 = getelementptr i8, ptr %load, i64 19112 %load139 = load i8, ptr %getelementptr138, align 1113 %getelementptr144 = getelementptr i8, ptr %load, i64 20114 %load145 = load i8, ptr %getelementptr144, align 1115 %getelementptr150 = getelementptr i8, ptr %load, i64 21116 %load151 = load i8, ptr %getelementptr150, align 1117 %getelementptr156 = getelementptr i8, ptr %load, i64 22118 %load157 = load i8, ptr %getelementptr156, align 1119 %getelementptr162 = getelementptr i8, ptr %load, i64 23120 %load163 = load i8, ptr %getelementptr162, align 1121 %getelementptr168 = getelementptr i8, ptr %load, i64 24122 %load169 = load i8, ptr %getelementptr168, align 1123 %getelementptr174 = getelementptr i8, ptr %load, i64 25124 %load175 = load i8, ptr %getelementptr174, align 1125 %getelementptr180 = getelementptr i8, ptr %load, i64 26126 %load181 = load i8, ptr %getelementptr180, align 1127 %getelementptr186 = getelementptr i8, ptr %load, i64 27128 %load187 = load i8, ptr %getelementptr186, align 1129 %getelementptr192 = getelementptr i8, ptr %load, i64 28130 %load193 = load i8, ptr %getelementptr192, align 1131 %getelementptr198 = getelementptr i8, ptr %load, i64 29132 %load199 = load i8, ptr %getelementptr198, align 1133 %getelementptr204 = getelementptr i8, ptr %load, i64 30134 %load205 = load i8, ptr %getelementptr204, align 1135 %getelementptr210 = getelementptr i8, ptr %load, i64 31136 %load211 = load i8, ptr %getelementptr210, align 1137 %alloca1.sroa.8.0.insert.ext = zext i8 %load67 to i64138 %alloca1.sroa.8.0.insert.shift = shl i64 %alloca1.sroa.8.0.insert.ext, 56139 %alloca1.sroa.7.0.insert.ext = zext i8 %load61 to i64140 %alloca1.sroa.7.0.insert.shift = shl i64 %alloca1.sroa.7.0.insert.ext, 48141 %alloca1.sroa.7.0.insert.insert = or i64 %alloca1.sroa.8.0.insert.shift, %alloca1.sroa.7.0.insert.shift142 %alloca1.sroa.6.0.insert.ext = zext i8 %load55 to i64143 %alloca1.sroa.6.0.insert.shift = shl i64 %alloca1.sroa.6.0.insert.ext, 40144 %alloca1.sroa.6.0.insert.insert = or i64 %alloca1.sroa.7.0.insert.insert, %alloca1.sroa.6.0.insert.shift145 %alloca1.sroa.5.0.insert.ext = zext i8 %load49 to i64146 %alloca1.sroa.5.0.insert.shift = shl i64 %alloca1.sroa.5.0.insert.ext, 32147 %alloca1.sroa.5.0.insert.insert = or i64 %alloca1.sroa.6.0.insert.insert, %alloca1.sroa.5.0.insert.shift148 %alloca1.sroa.4.0.insert.ext = zext i8 %load43 to i64149 %alloca1.sroa.4.0.insert.shift = shl i64 %alloca1.sroa.4.0.insert.ext, 24150 %alloca1.sroa.4.0.insert.insert = or i64 %alloca1.sroa.5.0.insert.insert, %alloca1.sroa.4.0.insert.shift151 %alloca1.sroa.3.0.insert.ext = zext i8 %load37 to i64152 %alloca1.sroa.3.0.insert.shift = shl i64 %alloca1.sroa.3.0.insert.ext, 16153 %alloca1.sroa.2.0.insert.ext = zext i8 %load31 to i64154 %alloca1.sroa.2.0.insert.shift = shl i64 %alloca1.sroa.2.0.insert.ext, 8155 %alloca1.sroa.2.0.insert.mask = or i64 %alloca1.sroa.4.0.insert.insert, %alloca1.sroa.3.0.insert.shift156 %alloca1.sroa.0.0.insert.ext = zext i8 %load28 to i64157 %alloca1.sroa.0.0.insert.mask = or i64 %alloca1.sroa.2.0.insert.mask, %alloca1.sroa.2.0.insert.shift158 %alloca1.sroa.0.0.insert.insert = or i64 %alloca1.sroa.0.0.insert.mask, %alloca1.sroa.0.0.insert.ext159 %call = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 %alloca1.sroa.0.0.insert.insert, i64 0, <16 x float> zeroinitializer, i32 0, i32 0, i32 0)160 %alloca1.sroa.17.8.insert.ext = zext i8 %load115 to i64161 %alloca1.sroa.17.8.insert.shift = shl i64 %alloca1.sroa.17.8.insert.ext, 56162 %alloca1.sroa.16.8.insert.ext = zext i8 %load109 to i64163 %alloca1.sroa.16.8.insert.shift = shl i64 %alloca1.sroa.16.8.insert.ext, 48164 %alloca1.sroa.16.8.insert.insert = or i64 %alloca1.sroa.17.8.insert.shift, %alloca1.sroa.16.8.insert.shift165 %alloca1.sroa.15.8.insert.ext = zext i8 %load103 to i64166 %alloca1.sroa.15.8.insert.shift = shl i64 %alloca1.sroa.15.8.insert.ext, 40167 %alloca1.sroa.15.8.insert.insert = or i64 %alloca1.sroa.16.8.insert.insert, %alloca1.sroa.15.8.insert.shift168 %alloca1.sroa.14.8.insert.ext = zext i8 %load97 to i64169 %alloca1.sroa.14.8.insert.shift = shl i64 %alloca1.sroa.14.8.insert.ext, 32170 %alloca1.sroa.14.8.insert.insert = or i64 %alloca1.sroa.15.8.insert.insert, %alloca1.sroa.14.8.insert.shift171 %alloca1.sroa.13.8.insert.ext = zext i8 %load91 to i64172 %alloca1.sroa.13.8.insert.shift = shl i64 %alloca1.sroa.13.8.insert.ext, 24173 %alloca1.sroa.13.8.insert.insert = or i64 %alloca1.sroa.14.8.insert.insert, %alloca1.sroa.13.8.insert.shift174 %alloca1.sroa.12.8.insert.ext = zext i8 %load85 to i64175 %alloca1.sroa.12.8.insert.shift = shl i64 %alloca1.sroa.12.8.insert.ext, 16176 %alloca1.sroa.11.8.insert.ext = zext i8 %load79 to i64177 %alloca1.sroa.11.8.insert.shift = shl i64 %alloca1.sroa.11.8.insert.ext, 8178 %alloca1.sroa.11.8.insert.mask = or i64 %alloca1.sroa.13.8.insert.insert, %alloca1.sroa.12.8.insert.shift179 %alloca1.sroa.9.8.insert.ext = zext i8 %load73 to i64180 %alloca1.sroa.9.8.insert.mask = or i64 %alloca1.sroa.11.8.insert.mask, %alloca1.sroa.11.8.insert.shift181 %alloca1.sroa.9.8.insert.insert = or i64 %alloca1.sroa.9.8.insert.mask, %alloca1.sroa.9.8.insert.ext182 %call225 = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 %alloca1.sroa.9.8.insert.insert, i64 0, <16 x float> %call, i32 0, i32 0, i32 0)183 %alloca1.sroa.26.16.insert.ext = zext i8 %load163 to i64184 %alloca1.sroa.26.16.insert.shift = shl i64 %alloca1.sroa.26.16.insert.ext, 56185 %alloca1.sroa.25.16.insert.ext = zext i8 %load157 to i64186 %alloca1.sroa.25.16.insert.shift = shl i64 %alloca1.sroa.25.16.insert.ext, 48187 %alloca1.sroa.25.16.insert.insert = or i64 %alloca1.sroa.26.16.insert.shift, %alloca1.sroa.25.16.insert.shift188 %alloca1.sroa.24.16.insert.ext = zext i8 %load151 to i64189 %alloca1.sroa.24.16.insert.shift = shl i64 %alloca1.sroa.24.16.insert.ext, 40190 %alloca1.sroa.24.16.insert.insert = or i64 %alloca1.sroa.25.16.insert.insert, %alloca1.sroa.24.16.insert.shift191 %alloca1.sroa.23.16.insert.ext = zext i8 %load145 to i64192 %alloca1.sroa.23.16.insert.shift = shl i64 %alloca1.sroa.23.16.insert.ext, 32193 %alloca1.sroa.23.16.insert.insert = or i64 %alloca1.sroa.24.16.insert.insert, %alloca1.sroa.23.16.insert.shift194 %alloca1.sroa.22.16.insert.ext = zext i8 %load139 to i64195 %alloca1.sroa.22.16.insert.shift = shl i64 %alloca1.sroa.22.16.insert.ext, 24196 %alloca1.sroa.22.16.insert.insert = or i64 %alloca1.sroa.23.16.insert.insert, %alloca1.sroa.22.16.insert.shift197 %alloca1.sroa.21.16.insert.ext = zext i8 %load133 to i64198 %alloca1.sroa.21.16.insert.shift = shl i64 %alloca1.sroa.21.16.insert.ext, 16199 %alloca1.sroa.20.16.insert.ext = zext i8 %load127 to i64200 %alloca1.sroa.20.16.insert.shift = shl i64 %alloca1.sroa.20.16.insert.ext, 8201 %alloca1.sroa.20.16.insert.mask = or i64 %alloca1.sroa.22.16.insert.insert, %alloca1.sroa.21.16.insert.shift202 %alloca1.sroa.18.16.insert.ext = zext i8 %load121 to i64203 %alloca1.sroa.18.16.insert.mask = or i64 %alloca1.sroa.20.16.insert.mask, %alloca1.sroa.20.16.insert.shift204 %alloca1.sroa.18.16.insert.insert = or i64 %alloca1.sroa.18.16.insert.mask, %alloca1.sroa.18.16.insert.ext205 %call230 = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 %alloca1.sroa.18.16.insert.insert, i64 0, <16 x float> %call225, i32 0, i32 0, i32 0)206 %alloca1.sroa.35.24.insert.ext = zext i8 %load211 to i64207 %alloca1.sroa.35.24.insert.shift = shl i64 %alloca1.sroa.35.24.insert.ext, 56208 %alloca1.sroa.34.24.insert.ext = zext i8 %load205 to i64209 %alloca1.sroa.34.24.insert.shift = shl i64 %alloca1.sroa.34.24.insert.ext, 48210 %alloca1.sroa.34.24.insert.insert = or i64 %alloca1.sroa.35.24.insert.shift, %alloca1.sroa.34.24.insert.shift211 %alloca1.sroa.33.24.insert.ext = zext i8 %load199 to i64212 %alloca1.sroa.33.24.insert.shift = shl i64 %alloca1.sroa.33.24.insert.ext, 40213 %alloca1.sroa.33.24.insert.insert = or i64 %alloca1.sroa.34.24.insert.insert, %alloca1.sroa.33.24.insert.shift214 %alloca1.sroa.32.24.insert.ext = zext i8 %load193 to i64215 %alloca1.sroa.32.24.insert.shift = shl i64 %alloca1.sroa.32.24.insert.ext, 32216 %alloca1.sroa.32.24.insert.insert = or i64 %alloca1.sroa.33.24.insert.insert, %alloca1.sroa.32.24.insert.shift217 %alloca1.sroa.31.24.insert.ext = zext i8 %load187 to i64218 %alloca1.sroa.31.24.insert.shift = shl i64 %alloca1.sroa.31.24.insert.ext, 24219 %alloca1.sroa.31.24.insert.insert = or i64 %alloca1.sroa.32.24.insert.insert, %alloca1.sroa.31.24.insert.shift220 %alloca1.sroa.30.24.insert.ext = zext i8 %load181 to i64221 %alloca1.sroa.30.24.insert.shift = shl i64 %alloca1.sroa.30.24.insert.ext, 16222 %alloca1.sroa.29.24.insert.ext = zext i8 %load175 to i64223 %alloca1.sroa.29.24.insert.shift = shl i64 %alloca1.sroa.29.24.insert.ext, 8224 %alloca1.sroa.29.24.insert.mask = or i64 %alloca1.sroa.31.24.insert.insert, %alloca1.sroa.30.24.insert.shift225 %alloca1.sroa.27.24.insert.ext = zext i8 %load169 to i64226 %alloca1.sroa.27.24.insert.mask = or i64 %alloca1.sroa.29.24.insert.mask, %alloca1.sroa.29.24.insert.shift227 %alloca1.sroa.27.24.insert.insert = or i64 %alloca1.sroa.27.24.insert.mask, %alloca1.sroa.27.24.insert.ext228 %call235 = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64 %alloca1.sroa.27.24.insert.insert, i64 0, <16 x float> %call230, i32 0, i32 0, i32 0)229 ret <16 x float> %call235230}231 232declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8(i64, i64, <16 x float>, i32 immarg, i32 immarg, i32 immarg) #0233 234attributes #0 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }235