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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s3 4; PR37098 - https://bugs.llvm.org/show_bug.cgi?id=370985 6define i32 @anyset_two_bit_mask(i32 %x) {7; CHECK-LABEL: @anyset_two_bit_mask(8; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 99; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 010; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i3211; CHECK-NEXT: ret i32 [[TMP3]]12;13 %s = lshr i32 %x, 314 %o = or i32 %s, %x15 %r = and i32 %o, 116 ret i32 %r17}18 19define <2 x i32> @anyset_two_bit_mask_uniform(<2 x i32> %x) {20; CHECK-LABEL: @anyset_two_bit_mask_uniform(21; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 9)22; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer23; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>24; CHECK-NEXT: ret <2 x i32> [[TMP3]]25;26 %s = lshr <2 x i32> %x, <i32 3, i32 3>27 %o = or <2 x i32> %s, %x28 %r = and <2 x i32> %o, <i32 1, i32 1>29 ret <2 x i32> %r30}31 32define i32 @anyset_four_bit_mask(i32 %x) {33; CHECK-LABEL: @anyset_four_bit_mask(34; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 29735; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 036; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i3237; CHECK-NEXT: ret i32 [[TMP3]]38;39 %t1 = lshr i32 %x, 340 %t2 = lshr i32 %x, 541 %t3 = lshr i32 %x, 842 %o1 = or i32 %t1, %x43 %o2 = or i32 %t2, %t344 %o3 = or i32 %o1, %o245 %r = and i32 %o3, 146 ret i32 %r47}48 49define <2 x i32> @anyset_four_bit_mask_uniform(<2 x i32> %x) {50; CHECK-LABEL: @anyset_four_bit_mask_uniform(51; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 297)52; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer53; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>54; CHECK-NEXT: ret <2 x i32> [[TMP3]]55;56 %t1 = lshr <2 x i32> %x, <i32 3, i32 3>57 %t2 = lshr <2 x i32> %x, <i32 5, i32 5>58 %t3 = lshr <2 x i32> %x, <i32 8, i32 8>59 %o1 = or <2 x i32> %t1, %x60 %o2 = or <2 x i32> %t2, %t361 %o3 = or <2 x i32> %o1, %o262 %r = and <2 x i32> %o3, <i32 1, i32 1>63 ret <2 x i32> %r64}65 66; We're not testing the LSB here, so all of the 'or' operands are shifts.67 68define i32 @anyset_three_bit_mask_all_shifted_bits(i32 %x) {69; CHECK-LABEL: @anyset_three_bit_mask_all_shifted_bits(70; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 29671; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 072; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i3273; CHECK-NEXT: ret i32 [[TMP3]]74;75 %t1 = lshr i32 %x, 376 %t2 = lshr i32 %x, 577 %t3 = lshr i32 %x, 878 %o2 = or i32 %t2, %t379 %o3 = or i32 %t1, %o280 %r = and i32 %o3, 181 ret i32 %r82}83 84define <2 x i32> @anyset_three_bit_mask_all_shifted_bits_uniform(<2 x i32> %x) {85; CHECK-LABEL: @anyset_three_bit_mask_all_shifted_bits_uniform(86; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 296)87; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer88; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>89; CHECK-NEXT: ret <2 x i32> [[TMP3]]90;91 %t1 = lshr <2 x i32> %x, <i32 3, i32 3>92 %t2 = lshr <2 x i32> %x, <i32 5, i32 5>93 %t3 = lshr <2 x i32> %x, <i32 8, i32 8>94 %o2 = or <2 x i32> %t2, %t395 %o3 = or <2 x i32> %t1, %o296 %r = and <2 x i32> %o3, <i32 1, i32 1>97 ret <2 x i32> %r98}99 100; Recognize the 'and' sibling pattern (all-bits-set). The 'and 1' may not be at the end.101 102define i32 @allset_two_bit_mask(i32 %x) {103; CHECK-LABEL: @allset_two_bit_mask(104; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 129105; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 129106; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32107; CHECK-NEXT: ret i32 [[TMP3]]108;109 %s = lshr i32 %x, 7110 %o = and i32 %s, %x111 %r = and i32 %o, 1112 ret i32 %r113}114 115define <2 x i32> @allset_two_bit_mask_uniform(<2 x i32> %x) {116; CHECK-LABEL: @allset_two_bit_mask_uniform(117; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 129)118; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 129)119; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>120; CHECK-NEXT: ret <2 x i32> [[TMP3]]121;122 %s = lshr <2 x i32> %x, <i32 7, i32 7>123 %o = and <2 x i32> %s, %x124 %r = and <2 x i32> %o, <i32 1, i32 1>125 ret <2 x i32> %r126}127 128define i64 @allset_four_bit_mask(i64 %x) {129; CHECK-LABEL: @allset_four_bit_mask(130; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 30131; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 30132; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64133; CHECK-NEXT: ret i64 [[TMP3]]134;135 %t1 = lshr i64 %x, 1136 %t2 = lshr i64 %x, 2137 %t3 = lshr i64 %x, 3138 %t4 = lshr i64 %x, 4139 %a1 = and i64 %t4, 1140 %a2 = and i64 %t2, %a1141 %a3 = and i64 %a2, %t1142 %r = and i64 %a3, %t3143 ret i64 %r144}145 146declare void @use(i32)147 148; negative test - extra use means the transform would increase instruction count149 150define i32 @allset_two_bit_mask_multiuse(i32 %x) {151; CHECK-LABEL: @allset_two_bit_mask_multiuse(152; CHECK-NEXT: [[S:%.*]] = lshr i32 [[X:%.*]], 7153; CHECK-NEXT: [[O:%.*]] = and i32 [[S]], [[X]]154; CHECK-NEXT: [[R:%.*]] = and i32 [[O]], 1155; CHECK-NEXT: call void @use(i32 [[O]])156; CHECK-NEXT: ret i32 [[R]]157;158 %s = lshr i32 %x, 7159 %o = and i32 %s, %x160 %r = and i32 %o, 1161 call void @use(i32 %o)162 ret i32 %r163}164 165; negative test - missing 'and 1' mask, so more than the low bit is used here166 167define i8 @allset_three_bit_mask_no_and1(i8 %x) {168; CHECK-LABEL: @allset_three_bit_mask_no_and1(169; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[X:%.*]], 1170; CHECK-NEXT: [[T2:%.*]] = lshr i8 [[X]], 2171; CHECK-NEXT: [[T3:%.*]] = lshr i8 [[X]], 3172; CHECK-NEXT: [[A2:%.*]] = and i8 [[T1]], [[T2]]173; CHECK-NEXT: [[R:%.*]] = and i8 [[A2]], [[T3]]174; CHECK-NEXT: ret i8 [[R]]175;176 %t1 = lshr i8 %x, 1177 %t2 = lshr i8 %x, 2178 %t3 = lshr i8 %x, 3179 %a2 = and i8 %t1, %t2180 %r = and i8 %a2, %t3181 ret i8 %r182}183 184; This test demonstrates that the transform can be large. If the implementation185; is slow or explosive (stack overflow due to recursion), it should be made efficient.186 187define i64 @allset_40_bit_mask(i64 %x) {188; CHECK-LABEL: @allset_40_bit_mask(189; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 2199023255550190; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2199023255550191; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64192; CHECK-NEXT: ret i64 [[TMP3]]193;194 %t1 = lshr i64 %x, 1195 %t2 = lshr i64 %x, 2196 %t3 = lshr i64 %x, 3197 %t4 = lshr i64 %x, 4198 %t5 = lshr i64 %x, 5199 %t6 = lshr i64 %x, 6200 %t7 = lshr i64 %x, 7201 %t8 = lshr i64 %x, 8202 %t9 = lshr i64 %x, 9203 %t10 = lshr i64 %x, 10204 %t11 = lshr i64 %x, 11205 %t12 = lshr i64 %x, 12206 %t13 = lshr i64 %x, 13207 %t14 = lshr i64 %x, 14208 %t15 = lshr i64 %x, 15209 %t16 = lshr i64 %x, 16210 %t17 = lshr i64 %x, 17211 %t18 = lshr i64 %x, 18212 %t19 = lshr i64 %x, 19213 %t20 = lshr i64 %x, 20214 %t21 = lshr i64 %x, 21215 %t22 = lshr i64 %x, 22216 %t23 = lshr i64 %x, 23217 %t24 = lshr i64 %x, 24218 %t25 = lshr i64 %x, 25219 %t26 = lshr i64 %x, 26220 %t27 = lshr i64 %x, 27221 %t28 = lshr i64 %x, 28222 %t29 = lshr i64 %x, 29223 %t30 = lshr i64 %x, 30224 %t31 = lshr i64 %x, 31225 %t32 = lshr i64 %x, 32226 %t33 = lshr i64 %x, 33227 %t34 = lshr i64 %x, 34228 %t35 = lshr i64 %x, 35229 %t36 = lshr i64 %x, 36230 %t37 = lshr i64 %x, 37231 %t38 = lshr i64 %x, 38232 %t39 = lshr i64 %x, 39233 %t40 = lshr i64 %x, 40234 235 %a1 = and i64 %t1, 1236 %a2 = and i64 %t2, %a1237 %a3 = and i64 %t3, %a2238 %a4 = and i64 %t4, %a3239 %a5 = and i64 %t5, %a4240 %a6 = and i64 %t6, %a5241 %a7 = and i64 %t7, %a6242 %a8 = and i64 %t8, %a7243 %a9 = and i64 %t9, %a8244 %a10 = and i64 %t10, %a9245 %a11 = and i64 %t11, %a10246 %a12 = and i64 %t12, %a11247 %a13 = and i64 %t13, %a12248 %a14 = and i64 %t14, %a13249 %a15 = and i64 %t15, %a14250 %a16 = and i64 %t16, %a15251 %a17 = and i64 %t17, %a16252 %a18 = and i64 %t18, %a17253 %a19 = and i64 %t19, %a18254 %a20 = and i64 %t20, %a19255 %a21 = and i64 %t21, %a20256 %a22 = and i64 %t22, %a21257 %a23 = and i64 %t23, %a22258 %a24 = and i64 %t24, %a23259 %a25 = and i64 %t25, %a24260 %a26 = and i64 %t26, %a25261 %a27 = and i64 %t27, %a26262 %a28 = and i64 %t28, %a27263 %a29 = and i64 %t29, %a28264 %a30 = and i64 %t30, %a29265 %a31 = and i64 %t31, %a30266 %a32 = and i64 %t32, %a31267 %a33 = and i64 %t33, %a32268 %a34 = and i64 %t34, %a33269 %a35 = and i64 %t35, %a34270 %a36 = and i64 %t36, %a35271 %a37 = and i64 %t37, %a36272 %a38 = and i64 %t38, %a37273 %a39 = and i64 %t39, %a38274 %a40 = and i64 %t40, %a39275 276 ret i64 %a40277}278 279; Verify that unsimplified code doesn't crash:280; https://bugs.llvm.org/show_bug.cgi?id=37446281 282define i32 @PR37446(i32 %x) {283; CHECK-LABEL: @PR37446(284; CHECK-NEXT: [[SHR:%.*]] = lshr i32 1, 33285; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 15286; CHECK-NEXT: [[AND1:%.*]] = and i32 [[AND]], [[X:%.*]]287; CHECK-NEXT: ret i32 [[AND1]]288;289 %shr = lshr i32 1, 33290 %and = and i32 %shr, 15291 %and1 = and i32 %and, %x292 ret i32 %and1293}294 295