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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s3 4define i16 @lshr_15(i16 %x) {5; CHECK-LABEL: @lshr_15(6; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], 157; CHECK-NEXT: ret i16 [[LSHR]]8;9 %zext = zext i16 %x to i3210 %lshr = lshr i32 %zext, 1511 %trunc = trunc i32 %lshr to i1612 ret i16 %trunc13}14 15; Negative test16 17define i16 @lshr_16(i16 %x) {18; CHECK-LABEL: @lshr_16(19; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i3220; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[ZEXT]], 1621; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i1622; CHECK-NEXT: ret i16 [[TRUNC]]23;24 %zext = zext i16 %x to i3225 %lshr = lshr i32 %zext, 1626 %trunc = trunc i32 %lshr to i1627 ret i16 %trunc28}29 30; Negative test31 32define i16 @lshr_var_shift_amount(i8 %x, i8 %amt) {33; CHECK-LABEL: @lshr_var_shift_amount(34; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i3235; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i3236; CHECK-NEXT: [[S:%.*]] = lshr i32 [[Z]], [[ZA]]37; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]38; CHECK-NEXT: [[S2:%.*]] = lshr i32 [[A]], 239; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i1640; CHECK-NEXT: ret i16 [[T]]41;42 %z = zext i8 %x to i3243 %za = zext i8 %amt to i3244 %s = lshr i32 %z, %za45 %a = add i32 %s, %z46 %s2 = lshr i32 %a, 247 %t = trunc i32 %s2 to i1648 ret i16 %t49}50 51define i16 @lshr_var_bounded_shift_amount(i8 %x, i8 %amt) {52; CHECK-LABEL: @lshr_var_bounded_shift_amount(53; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i1654; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i1655; CHECK-NEXT: [[ZA2:%.*]] = and i16 [[ZA]], 1556; CHECK-NEXT: [[S:%.*]] = lshr i16 [[Z]], [[ZA2]]57; CHECK-NEXT: [[A:%.*]] = add i16 [[S]], [[Z]]58; CHECK-NEXT: [[S2:%.*]] = lshr i16 [[A]], 259; CHECK-NEXT: ret i16 [[S2]]60;61 %z = zext i8 %x to i3262 %za = zext i8 %amt to i3263 %za2 = and i32 %za, 1564 %s = lshr i32 %z, %za265 %a = add i32 %s, %z66 %s2 = lshr i32 %a, 267 %t = trunc i32 %s2 to i1668 ret i16 %t69}70 71; Negative test72 73define i32 @lshr_check_no_overflow(i32 %x, i16 %amt) {74; CHECK-LABEL: @lshr_check_no_overflow(75; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i6476; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i6477; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 429496729578; CHECK-NEXT: [[SHL:%.*]] = lshr i64 [[ZEXT]], [[AND]]79; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i3280; CHECK-NEXT: ret i32 [[TRUNC]]81;82 %zext = zext i32 %x to i6483 %sext = sext i16 %amt to i6484 %and = and i64 %sext, 429496729585 %shl = lshr i64 %zext, %and86 %trunc = trunc i64 %shl to i3287 ret i32 %trunc88}89 90define void @lshr_big_dag(ptr %a, i8 %b, i8 %c) {91; CHECK-LABEL: @lshr_big_dag(92; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i1693; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i1694; CHECK-NEXT: [[ADD1:%.*]] = add i16 [[ZEXT1]], [[ZEXT2]]95; CHECK-NEXT: [[SFT1:%.*]] = and i16 [[ADD1]], 1596; CHECK-NEXT: [[SHR1:%.*]] = lshr i16 [[ADD1]], [[SFT1]]97; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]98; CHECK-NEXT: [[SFT2:%.*]] = and i16 [[ADD2]], 799; CHECK-NEXT: [[SHR2:%.*]] = lshr i16 [[ADD2]], [[SFT2]]100; CHECK-NEXT: store i16 [[SHR2]], ptr [[A:%.*]], align 2101; CHECK-NEXT: ret void102;103 %zext1 = zext i8 %b to i32104 %zext2 = zext i8 %c to i32105 %add1 = add i32 %zext1, %zext2106 %sft1 = and i32 %add1, 15107 %shr1 = lshr i32 %add1, %sft1108 %add2 = add i32 %add1, %shr1109 %sft2 = and i32 %add2, 7110 %shr2 = lshr i32 %add2, %sft2111 %trunc = trunc i32 %shr2 to i16112 store i16 %trunc, ptr %a, align 2113 ret void114}115 116; Negative test117 118define i8 @lshr_check_not_i8_trunc(i16 %x) {119; CHECK-LABEL: @lshr_check_not_i8_trunc(120; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], 1121; CHECK-NEXT: [[ZEXT2:%.*]] = zext i16 [[LSHR]] to i32122; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[ZEXT2]], 2123; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i8124; CHECK-NEXT: ret i8 [[TRUNC]]125;126 %lshr = lshr i16 %x, 1127 %zext2 = zext i16 %lshr to i32128 %lshr2 = lshr i32 %zext2, 2129 %trunc = trunc i32 %lshr2 to i8130 ret i8 %trunc131}132 133define <2 x i16> @lshr_vector(<2 x i8> %x) {134; CHECK-LABEL: @lshr_vector(135; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>136; CHECK-NEXT: [[ZA:%.*]] = and <2 x i16> [[Z]], <i16 7, i16 8>137; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[Z]], [[ZA]]138; CHECK-NEXT: [[A:%.*]] = add <2 x i16> [[S]], [[Z]]139; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i16> [[A]], <i16 4, i16 5>140; CHECK-NEXT: ret <2 x i16> [[S2]]141;142 %z = zext <2 x i8> %x to <2 x i32>143 %za = and <2 x i32> %z, <i32 7, i32 8>144 %s = lshr <2 x i32> %z, %za145 %a = add <2 x i32> %s, %z146 %s2 = lshr <2 x i32> %a, <i32 4, i32 5>147 %t = trunc <2 x i32> %s2 to <2 x i16>148 ret <2 x i16> %t149}150 151; Negative test - can only fold to <2 x i16>, requiring new vector type152 153define <2 x i8> @lshr_vector_no_new_vector_type(<2 x i8> %x) {154; CHECK-LABEL: @lshr_vector_no_new_vector_type(155; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>156; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>157; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]158; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]159; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 4, i32 5>160; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i8>161; CHECK-NEXT: ret <2 x i8> [[T]]162;163 %z = zext <2 x i8> %x to <2 x i32>164 %za = and <2 x i32> %z, <i32 7, i32 8>165 %s = lshr <2 x i32> %z, %za166 %a = add <2 x i32> %s, %z167 %s2 = lshr <2 x i32> %a, <i32 4, i32 5>168 %t = trunc <2 x i32> %s2 to <2 x i8>169 ret <2 x i8> %t170}171 172; Negative test173 174define <2 x i16> @lshr_vector_large_shift_amount(<2 x i8> %x) {175; CHECK-LABEL: @lshr_vector_large_shift_amount(176; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>177; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>178; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]179; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]180; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 16, i32 5>181; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>182; CHECK-NEXT: ret <2 x i16> [[T]]183;184 %z = zext <2 x i8> %x to <2 x i32>185 %za = and <2 x i32> %z, <i32 7, i32 8>186 %s = lshr <2 x i32> %z, %za187 %a = add <2 x i32> %s, %z188 %s2 = lshr <2 x i32> %a, <i32 16, i32 5>189 %t = trunc <2 x i32> %s2 to <2 x i16>190 ret <2 x i16> %t191}192 193define i16 @lshr_exact(i16 %x) {194; CHECK-LABEL: @lshr_exact(195; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[X:%.*]], 15196; CHECK-NEXT: ret i16 [[LSHR]]197;198 %zext = zext i16 %x to i32199 %lshr = lshr exact i32 %zext, 15200 %trunc = trunc i32 %lshr to i16201 ret i16 %trunc202}203 204; Negative test205 206define i16 @lshr_negative_operand(i16 %x) {207; CHECK-LABEL: @lshr_negative_operand(208; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32209; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[ZEXT]]210; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[XOR]], 2211; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16212; CHECK-NEXT: ret i16 [[TRUNC]]213;214 %zext = zext i16 %x to i32215 %xor = xor i32 -1, %zext216 %lshr2 = lshr i32 %xor, 2217 %trunc = trunc i32 %lshr2 to i16218 ret i16 %trunc219}220 221; We may encounter unoptimized IR as below,222; so don't crash by assuming that we can223; apply instruction flags (exact) if there224; is no instruction.225 226define i8 @non_canonical_crash() {227; CHECK-LABEL: @non_canonical_crash(228; CHECK-NEXT: ret i8 8229;230 %sh = lshr i32 33, 2231 %tr = trunc i32 %sh to i8232 ret i8 %tr233}234