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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s3 4define dso_local i16 @cmp_select_sext_const(i8 %a) !prof !0 {5; CHECK-LABEL: @cmp_select_sext_const(6; CHECK: !prof [[PROF_0:![0-9]+]] {7; CHECK-NEXT: entry:8; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i329; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10910; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 109, i32 [[CONV]], !prof [[PROF_1:![0-9]+]]11; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i1612; CHECK-NEXT: ret i16 [[CONV4]]13;14entry:15 %conv = sext i8 %a to i3216 %cmp = icmp slt i32 %conv, 10917 %cond = select i1 %cmp, i32 109, i32 %conv, !prof !118 %conv4 = trunc i32 %cond to i1619 ret i16 %conv420}21 22define dso_local i16 @cmp_select_sext(i8 %a, i8 %b) {23; CHECK-LABEL: @cmp_select_sext(24; CHECK-NEXT: entry:25; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i3226; CHECK-NEXT: [[CONV2:%.*]] = sext i8 [[B:%.*]] to i3227; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[CONV2]]28; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]29; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i1630; CHECK-NEXT: ret i16 [[CONV4]]31;32entry:33 %conv = sext i8 %a to i3234 %conv2 = sext i8 %b to i3235 %cmp = icmp slt i32 %conv, %conv236 %cond = select i1 %cmp, i32 %conv2, i32 %conv37 %conv4 = trunc i32 %cond to i1638 ret i16 %conv439}40 41define dso_local i16 @cmp_select_zext(i8 %a, i8 %b) {42; CHECK-LABEL: @cmp_select_zext(43; CHECK-NEXT: entry:44; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i3245; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[B:%.*]] to i3246; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[CONV2]]47; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]48; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i1649; CHECK-NEXT: ret i16 [[CONV4]]50;51entry:52 %conv = zext i8 %a to i3253 %conv2 = zext i8 %b to i3254 %cmp = icmp slt i32 %conv, %conv255 %cond = select i1 %cmp, i32 %conv2, i32 %conv56 %conv4 = trunc i32 %cond to i1657 ret i16 %conv458}59 60define dso_local i16 @cmp_select_zext_sext(i8 %a, i8 %b) {61; CHECK-LABEL: @cmp_select_zext_sext(62; CHECK-NEXT: entry:63; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i3264; CHECK-NEXT: [[CONV2:%.*]] = sext i8 [[B:%.*]] to i3265; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[CONV2]]66; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]67; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i1668; CHECK-NEXT: ret i16 [[CONV4]]69;70entry:71 %conv = zext i8 %a to i3272 %conv2 = sext i8 %b to i3273 %cmp = icmp slt i32 %conv, %conv274 %cond = select i1 %cmp, i32 %conv2, i32 %conv75 %conv4 = trunc i32 %cond to i1676 ret i16 %conv477}78 79define dso_local i16 @cmp_select_zext_sext_diffOrigTy(i8 %a, i16 %b) {80; CHECK-LABEL: @cmp_select_zext_sext_diffOrigTy(81; CHECK-NEXT: entry:82; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i3283; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[B:%.*]] to i3284; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], [[CONV2]]85; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]86; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i1687; CHECK-NEXT: ret i16 [[CONV4]]88;89entry:90 %conv = zext i8 %a to i3291 %conv2 = sext i16 %b to i3292 %cmp = icmp slt i32 %conv, %conv293 %cond = select i1 %cmp, i32 %conv2, i32 %conv94 %conv4 = trunc i32 %cond to i1695 ret i16 %conv496}97 98define dso_local i16 @my_abs_sext(i8 %a) {99; CHECK-LABEL: @my_abs_sext(100; CHECK-NEXT: entry:101; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i32102; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 0103; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[CONV]]104; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[CONV]]105; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16106; CHECK-NEXT: ret i16 [[CONV4]]107;108entry:109 %conv = sext i8 %a to i32110 %cmp = icmp slt i32 %conv, 0111 %sub = sub nsw i32 0, %conv112 %cond = select i1 %cmp, i32 %sub, i32 %conv113 %conv4 = trunc i32 %cond to i16114 ret i16 %conv4115}116 117define dso_local i16 @my_abs_zext(i8 %a) {118; CHECK-LABEL: @my_abs_zext(119; CHECK-NEXT: entry:120; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32121; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 0122; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[CONV]]123; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[CONV]]124; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16125; CHECK-NEXT: ret i16 [[CONV4]]126;127entry:128 %conv = zext i8 %a to i32129 %cmp = icmp slt i32 %conv, 0130 %sub = sub nsw i32 0, %conv131 %cond = select i1 %cmp, i32 %sub, i32 %conv132 %conv4 = trunc i32 %cond to i16133 ret i16 %conv4134}135 136define dso_local i16 @select_sext(i8 %a, i1 %cond) {137; CHECK-LABEL: @select_sext(138; CHECK-NEXT: entry:139; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i16140; CHECK-NEXT: [[SUB:%.*]] = sub i16 0, [[CONV]]141; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[SUB]], i16 [[CONV]]142; CHECK-NEXT: ret i16 [[SEL]]143;144entry:145 %conv = sext i8 %a to i32146 %sub = sub nsw i32 0, %conv147 %sel = select i1 %cond, i32 %sub, i32 %conv148 %conv4 = trunc i32 %sel to i16149 ret i16 %conv4150}151 152define dso_local i16 @select_zext(i8 %a, i1 %cond) {153; CHECK-LABEL: @select_zext(154; CHECK-NEXT: entry:155; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i16156; CHECK-NEXT: [[SUB:%.*]] = sub i16 0, [[CONV]]157; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[SUB]], i16 [[CONV]]158; CHECK-NEXT: ret i16 [[SEL]]159;160entry:161 %conv = zext i8 %a to i32162 %sub = sub nsw i32 0, %conv163 %sel = select i1 %cond, i32 %sub, i32 %conv164 %conv4 = trunc i32 %sel to i16165 ret i16 %conv4166}167 168define i16 @cmp_select_signed_const_i16Const_noTransformation(i8 %a) {169; CHECK-LABEL: @cmp_select_signed_const_i16Const_noTransformation(170; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i32171; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 32768172; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 32768, i32 [[CONV]]173; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16174; CHECK-NEXT: ret i16 [[CONV4]]175;176 %conv = sext i8 %a to i32177 %cmp = icmp slt i32 %conv, 32768178 %cond = select i1 %cmp, i32 32768, i32 %conv179 %conv4 = trunc i32 %cond to i16180 ret i16 %conv4181}182 183define i16 @cmp_select_unsigned_const_i16Const(i8 %a) {184; CHECK-LABEL: @cmp_select_unsigned_const_i16Const(185; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32186; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[CONV]], 32768187; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 32768, i32 [[CONV]]188; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16189; CHECK-NEXT: ret i16 [[CONV4]]190;191 %conv = zext i8 %a to i32192 %cmp = icmp ult i32 %conv, 32768193 %cond = select i1 %cmp, i32 32768, i32 %conv194 %conv4 = trunc i32 %cond to i16195 ret i16 %conv4196}197 198define i16 @cmp_select_unsigned_const_i16Const_noTransformation(i8 %a) {199; CHECK-LABEL: @cmp_select_unsigned_const_i16Const_noTransformation(200; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32201; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[CONV]], 65536202; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 65536, i32 [[CONV]]203; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16204; CHECK-NEXT: ret i16 [[CONV4]]205;206 %conv = zext i8 %a to i32207 %cmp = icmp ult i32 %conv, 65536208 %cond = select i1 %cmp, i32 65536, i32 %conv209 %conv4 = trunc i32 %cond to i16210 ret i16 %conv4211}212 213!0 = !{!"function_entry_count", i64 1000}214!1 = !{!"branch_weights", i32 2, i32 3}215; CHECK: [[PROF_0]] = !{!"function_entry_count", i64 1000}216; CHECK: [[PROF_1]] = !{!"branch_weights", i32 2, i32 3}217