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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=aggressive-instcombine,instcombine -S | FileCheck %s3 4; Ladder4 variant. https://alive2.llvm.org/ce/z/tExFRs5define i32 @mul_ladder4(i32 %x, i32 %y) {6; CHECK-LABEL: define i32 @mul_ladder4(7; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[X]] to i6410; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y]] to i6411; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]12; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3213; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i64 [[TMP3]] to i3214; CHECK-NEXT: ret i32 [[ADD19]]15;16entry:17 %xl = and i32 %x, 6553518 %xh = lshr i32 %x, 1619 %yl = and i32 %y, 6553520 %yh = lshr i32 %y, 1621 %mulll = mul nuw i32 %xl, %yl22 %mullh = mul nuw i32 %xl, %yh23 %mulhl = mul nuw i32 %xh, %yl24 %mulhh = mul nuw i32 %xh, %yh25 %shr8 = lshr i32 %mulll, 1626 %conv10 = and i32 %mullh, 6553527 %add = add nuw nsw i32 %shr8, %conv1028 %conv12 = and i32 %mulhl, 6553529 %add13 = add nuw nsw i32 %add, %conv1230 %shr14 = lshr i32 %add13, 1631 %shr15 = lshr i32 %mullh, 1632 %add16 = add nuw i32 %mulhh, %shr1533 %shr17 = lshr i32 %mulhl, 1634 %add18 = add nuw i32 %add16, %shr1735 %add19 = add nuw i32 %add18, %shr1436 ret i32 %add1937}38 39define <2 x i32> @mul_ladder4_v2i32(<2 x i32> %x, <2 x i32> %y) {40; CHECK-LABEL: define <2 x i32> @mul_ladder4_v2i32(41; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) {42; CHECK-NEXT: [[ENTRY:.*:]]43; CHECK-NEXT: [[TMP0:%.*]] = zext <2 x i32> [[X]] to <2 x i64>44; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[Y]] to <2 x i64>45; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <2 x i64> [[TMP0]], [[TMP1]]46; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i64> [[TMP2]], splat (i64 32)47; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw <2 x i64> [[TMP3]] to <2 x i32>48; CHECK-NEXT: ret <2 x i32> [[ADD19]]49;50entry:51 %xl = and <2 x i32> %x, <i32 65535, i32 65535>52 %xh = lshr <2 x i32> %x, <i32 16, i32 16>53 %yl = and <2 x i32> %y, <i32 65535, i32 65535>54 %yh = lshr <2 x i32> %y, <i32 16, i32 16>55 %mulll = mul nuw <2 x i32> %xl, %yl56 %mullh = mul nuw <2 x i32> %xl, %yh57 %mulhl = mul nuw <2 x i32> %xh, %yl58 %mulhh = mul nuw <2 x i32> %xh, %yh59 %shr8 = lshr <2 x i32> %mulll, <i32 16, i32 16>60 %conv10 = and <2 x i32> %mullh, <i32 65535, i32 65535>61 %add = add nuw nsw <2 x i32> %shr8, %conv1062 %conv12 = and <2 x i32> %mulhl, <i32 65535, i32 65535>63 %add13 = add nuw nsw <2 x i32> %add, %conv1264 %shr14 = lshr <2 x i32> %add13, <i32 16, i32 16>65 %shr15 = lshr <2 x i32> %mullh, <i32 16, i32 16>66 %add16 = add nuw <2 x i32> %mulhh, %shr1567 %shr17 = lshr <2 x i32> %mulhl, <i32 16, i32 16>68 %add18 = add nuw <2 x i32> %add16, %shr1769 %add19 = add nuw <2 x i32> %add18, %shr1470 ret <2 x i32> %add1971}72 73define i128 @mul_ladder4_i128(i128 %x, i128 %y) {74; CHECK-LABEL: define i128 @mul_ladder4_i128(75; CHECK-SAME: i128 [[X:%.*]], i128 [[Y:%.*]]) {76; CHECK-NEXT: [[ENTRY:.*:]]77; CHECK-NEXT: [[TMP0:%.*]] = zext i128 [[X]] to i25678; CHECK-NEXT: [[TMP1:%.*]] = zext i128 [[Y]] to i25679; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i256 [[TMP0]], [[TMP1]]80; CHECK-NEXT: [[TMP3:%.*]] = lshr i256 [[TMP2]], 12881; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i256 [[TMP3]] to i12882; CHECK-NEXT: ret i128 [[ADD19]]83;84entry:85 %xl = and i128 %x, u0xffffffffffffffff86 %xh = lshr i128 %x, 6487 %yl = and i128 %y, u0xffffffffffffffff88 %yh = lshr i128 %y, 6489 %mulll = mul nuw i128 %xl, %yl90 %mullh = mul nuw i128 %xl, %yh91 %mulhl = mul nuw i128 %xh, %yl92 %mulhh = mul nuw i128 %xh, %yh93 %shr8 = lshr i128 %mulll, 6494 %conv10 = and i128 %mullh, u0xffffffffffffffff95 %add = add nuw nsw i128 %shr8, %conv1096 %conv12 = and i128 %mulhl, u0xffffffffffffffff97 %add13 = add nuw nsw i128 %add, %conv1298 %shr14 = lshr i128 %add13, 6499 %shr15 = lshr i128 %mullh, 64100 %add16 = add nuw i128 %mulhh, %shr15101 %shr17 = lshr i128 %mulhl, 64102 %add18 = add nuw i128 %add16, %shr17103 %add19 = add nuw i128 %add18, %shr14104 ret i128 %add19105}106 107define i32 @mul_ladder4_commutted(i32 %x, i32 %y) {108; CHECK-LABEL: define i32 @mul_ladder4_commutted(109; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {110; CHECK-NEXT: [[ENTRY:.*:]]111; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[Y]] to i64112; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X]] to i64113; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]114; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 32115; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i64 [[TMP3]] to i32116; CHECK-NEXT: ret i32 [[ADD19]]117;118entry:119 %xl = and i32 %x, 65535120 %xh = lshr i32 %x, 16121 %yl = and i32 %y, 65535122 %yh = lshr i32 %y, 16123 %mulll = mul nuw i32 %yl, %xl124 %mullh = mul nuw i32 %yh, %xl125 %mulhl = mul nuw i32 %yl, %xh126 %mulhh = mul nuw i32 %yh, %xh127 %shr8 = lshr i32 %mulll, 16128 %conv10 = and i32 %mullh, 65535129 %add = add nuw nsw i32 %conv10, %shr8130 %conv12 = and i32 %mulhl, 65535131 %add13 = add nuw nsw i32 %conv12, %add132 %shr14 = lshr i32 %add13, 16133 %shr15 = lshr i32 %mullh, 16134 %shr17 = lshr i32 %mulhl, 16135 %add16 = add nuw i32 %shr14, %shr17136 %add18 = add nuw i32 %add16, %shr15137 %add19 = add nuw i32 %mulhh, %add18138 ret i32 %add19139}140 141define i32 @mul_ladder4_swap_hl_lh(i32 %x, i32 %y) {142; CHECK-LABEL: define i32 @mul_ladder4_swap_hl_lh(143; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {144; CHECK-NEXT: [[ENTRY:.*:]]145; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[X]] to i64146; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y]] to i64147; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]148; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 32149; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i64 [[TMP3]] to i32150; CHECK-NEXT: ret i32 [[ADD19]]151;152entry:153 %xl = and i32 %x, 65535154 %xh = lshr i32 %x, 16155 %yl = and i32 %y, 65535156 %yh = lshr i32 %y, 16157 %mulll = mul nuw i32 %xl, %yl158 %mullh = mul nuw i32 %xl, %yh159 %mulhl = mul nuw i32 %xh, %yl160 %mulhh = mul nuw i32 %xh, %yh161 %shr8 = lshr i32 %mulll, 16162 %conv10 = and i32 %mulhl, 65535163 %add = add nuw nsw i32 %shr8, %conv10164 %conv12 = and i32 %mullh, 65535165 %add13 = add nuw nsw i32 %add, %conv12166 %shr14 = lshr i32 %add13, 16167 %shr15 = lshr i32 %mulhl, 16168 %add16 = add nuw i32 %mulhh, %shr15169 %shr17 = lshr i32 %mullh, 16170 %add18 = add nuw i32 %add16, %shr17171 %add19 = add nuw i32 %add18, %shr14172 ret i32 %add19173}174 175 176; Negative tests177 178define i32 @mul_ladder4_notlhhl(i32 %x, i32 %y) {179; CHECK-LABEL: define i32 @mul_ladder4_notlhhl(180; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {181; CHECK-NEXT: [[ENTRY:.*:]]182; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535183; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16184; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535185; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16186; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[XL]], [[YL]]187; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[XH]], [[YL]]188; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[XH]], [[YH]]189; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16190; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULHL]], 65535191; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[SHR8]], [[CONV10]]192; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535193; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[ADD]], [[CONV12]]194; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16195; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL]], 16196; CHECK-NEXT: [[ADD16:%.*]] = add nuw i32 [[MULHH]], [[SHR15]]197; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16198; CHECK-NEXT: [[ADD18:%.*]] = add nuw i32 [[ADD16]], [[SHR17]]199; CHECK-NEXT: [[ADD19:%.*]] = add nuw i32 [[ADD18]], [[SHR14]]200; CHECK-NEXT: ret i32 [[ADD19]]201;202entry:203 %xl = and i32 %x, 65535204 %xh = lshr i32 %x, 16205 %yl = and i32 %y, 65535206 %yh = lshr i32 %y, 16207 %mulll = mul nuw i32 %xl, %yl208 %mullh = mul nuw i32 %xl, %yh209 %mulhl = mul nuw i32 %xh, %yl210 %mulhh = mul nuw i32 %xh, %yh211 %shr8 = lshr i32 %mulll, 16212 %conv10 = and i32 %mulhl, 65535213 %add = add nuw nsw i32 %shr8, %conv10214 %conv12 = and i32 %mulhl, 65535215 %add13 = add nuw nsw i32 %add, %conv12216 %shr14 = lshr i32 %add13, 16217 %shr15 = lshr i32 %mulhl, 16218 %add16 = add nuw i32 %mulhh, %shr15219 %shr17 = lshr i32 %mulhl, 16220 %add18 = add nuw i32 %add16, %shr17221 %add19 = add nuw i32 %add18, %shr14222 ret i32 %add19223}224 225 226 227 228 229 230; Extra uses231 232define i32 @mul_ladder4_use_add13(i32 %x, i32 %y) {233; CHECK-LABEL: define i32 @mul_ladder4_use_add13(234; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {235; CHECK-NEXT: [[ENTRY:.*:]]236; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535237; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16238; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535239; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16240; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]241; CHECK-NEXT: [[MULLH:%.*]] = mul nuw i32 [[YH]], [[XL]]242; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]243; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]244; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16245; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULLH]], 65535246; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV10]], [[SHR8]]247; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535248; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]249; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16250; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULLH]], 16251; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16252; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]253; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]254; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]255; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[ADD13]])256; CHECK-NEXT: ret i32 [[ADD19]]257;258entry:259 %xl = and i32 %x, 65535260 %xh = lshr i32 %x, 16261 %yl = and i32 %y, 65535262 %yh = lshr i32 %y, 16263 %mulll = mul nuw i32 %yl, %xl264 %mullh = mul nuw i32 %yh, %xl265 %mulhl = mul nuw i32 %yl, %xh266 %mulhh = mul nuw i32 %yh, %xh267 %shr8 = lshr i32 %mulll, 16268 %conv10 = and i32 %mullh, 65535269 %add = add nuw nsw i32 %conv10, %shr8270 %conv12 = and i32 %mulhl, 65535271 %add13 = add nuw nsw i32 %conv12, %add272 %shr14 = lshr i32 %add13, 16273 %shr15 = lshr i32 %mullh, 16274 %shr17 = lshr i32 %mulhl, 16275 %add16 = add i32 %shr14, %shr17276 %add18 = add i32 %add16, %shr15277 %add19 = add i32 %mulhh, %add18278 call void (...) @llvm.fake.use(i32 %add13)279 ret i32 %add19280}281 282define i32 @mul_ladder4_use_conv12(i32 %x, i32 %y) {283; CHECK-LABEL: define i32 @mul_ladder4_use_conv12(284; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {285; CHECK-NEXT: [[ENTRY:.*:]]286; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535287; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16288; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535289; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16290; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]291; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YH]], [[XL]]292; CHECK-NEXT: [[MULHL1:%.*]] = mul nuw i32 [[YL]], [[XH]]293; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]294; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16295; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535296; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV12]], [[SHR8]]297; CHECK-NEXT: [[CONV13:%.*]] = and i32 [[MULHL1]], 65535298; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV13]], [[ADD]]299; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16300; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL]], 16301; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL1]], 16302; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]303; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]304; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]305; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[CONV13]])306; CHECK-NEXT: ret i32 [[ADD19]]307;308entry:309 %xl = and i32 %x, 65535310 %xh = lshr i32 %x, 16311 %yl = and i32 %y, 65535312 %yh = lshr i32 %y, 16313 %mulll = mul nuw i32 %yl, %xl314 %mullh = mul nuw i32 %yh, %xl315 %mulhl = mul nuw i32 %yl, %xh316 %mulhh = mul nuw i32 %yh, %xh317 %shr8 = lshr i32 %mulll, 16318 %conv10 = and i32 %mullh, 65535319 %add = add nuw nsw i32 %conv10, %shr8320 %conv12 = and i32 %mulhl, 65535321 %add13 = add nuw nsw i32 %conv12, %add322 %shr14 = lshr i32 %add13, 16323 %shr15 = lshr i32 %mullh, 16324 %shr17 = lshr i32 %mulhl, 16325 %add16 = add i32 %shr14, %shr17326 %add18 = add i32 %add16, %shr15327 %add19 = add i32 %mulhh, %add18328 call void (...) @llvm.fake.use(i32 %conv12)329 ret i32 %add19330}331 332define i32 @mul_ladder4_use_u0(i32 %x, i32 %y) {333; CHECK-LABEL: define i32 @mul_ladder4_use_u0(334; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {335; CHECK-NEXT: [[ENTRY:.*:]]336; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535337; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16338; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535339; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16340; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]341; CHECK-NEXT: [[MULHL1:%.*]] = mul nuw i32 [[YH]], [[XL]]342; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]343; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]344; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16345; CHECK-NEXT: [[CONV13:%.*]] = and i32 [[MULHL1]], 65535346; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV13]], [[SHR8]]347; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535348; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]349; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16350; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL1]], 16351; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16352; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]353; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]354; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]355; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[ADD]])356; CHECK-NEXT: ret i32 [[ADD19]]357;358entry:359 %xl = and i32 %x, 65535360 %xh = lshr i32 %x, 16361 %yl = and i32 %y, 65535362 %yh = lshr i32 %y, 16363 %mulll = mul nuw i32 %yl, %xl364 %mullh = mul nuw i32 %yh, %xl365 %mulhl = mul nuw i32 %yl, %xh366 %mulhh = mul nuw i32 %yh, %xh367 %shr8 = lshr i32 %mulll, 16368 %conv10 = and i32 %mullh, 65535369 %add = add nuw nsw i32 %conv10, %shr8370 %conv12 = and i32 %mulhl, 65535371 %add13 = add nuw nsw i32 %conv12, %add372 %shr14 = lshr i32 %add13, 16373 %shr15 = lshr i32 %mullh, 16374 %shr17 = lshr i32 %mulhl, 16375 %add16 = add i32 %shr14, %shr17376 %add18 = add i32 %add16, %shr15377 %add19 = add i32 %mulhh, %add18378 call void (...) @llvm.fake.use(i32 %add)379 ret i32 %add19380}381 382define i32 @mul_ladder4_use_hl(i32 %x, i32 %y) {383; CHECK-LABEL: define i32 @mul_ladder4_use_hl(384; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {385; CHECK-NEXT: [[ENTRY:.*:]]386; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535387; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16388; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535389; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16390; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]391; CHECK-NEXT: [[MULLH:%.*]] = mul nuw i32 [[YH]], [[XL]]392; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]393; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]394; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16395; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULLH]], 65535396; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV10]], [[SHR8]]397; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535398; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]399; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16400; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULLH]], 16401; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16402; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]403; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]404; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]405; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[MULHL]])406; CHECK-NEXT: ret i32 [[ADD19]]407;408entry:409 %xl = and i32 %x, 65535410 %xh = lshr i32 %x, 16411 %yl = and i32 %y, 65535412 %yh = lshr i32 %y, 16413 %mulll = mul nuw i32 %yl, %xl414 %mullh = mul nuw i32 %yh, %xl415 %mulhl = mul nuw i32 %yl, %xh416 %mulhh = mul nuw i32 %yh, %xh417 %shr8 = lshr i32 %mulll, 16418 %conv10 = and i32 %mullh, 65535419 %add = add nuw nsw i32 %conv10, %shr8420 %conv12 = and i32 %mulhl, 65535421 %add13 = add nuw nsw i32 %conv12, %add422 %shr14 = lshr i32 %add13, 16423 %shr15 = lshr i32 %mullh, 16424 %shr17 = lshr i32 %mulhl, 16425 %add16 = add i32 %shr14, %shr17426 %add18 = add i32 %add16, %shr15427 %add19 = add i32 %mulhh, %add18428 call void (...) @llvm.fake.use(i32 %mulhl)429 ret i32 %add19430}431 432define i32 @mul_ladder4_use_lh(i32 %x, i32 %y) {433; CHECK-LABEL: define i32 @mul_ladder4_use_lh(434; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {435; CHECK-NEXT: [[ENTRY:.*:]]436; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535437; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16438; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535439; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16440; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]441; CHECK-NEXT: [[MULLH:%.*]] = mul nuw i32 [[YH]], [[XL]]442; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]443; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]444; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16445; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULLH]], 65535446; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV10]], [[SHR8]]447; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535448; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]449; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16450; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULLH]], 16451; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16452; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]453; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]454; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]455; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[MULLH]])456; CHECK-NEXT: ret i32 [[ADD19]]457;458entry:459 %xl = and i32 %x, 65535460 %xh = lshr i32 %x, 16461 %yl = and i32 %y, 65535462 %yh = lshr i32 %y, 16463 %mulll = mul nuw i32 %yl, %xl464 %mullh = mul nuw i32 %yh, %xl465 %mulhl = mul nuw i32 %yl, %xh466 %mulhh = mul nuw i32 %yh, %xh467 %shr8 = lshr i32 %mulll, 16468 %conv10 = and i32 %mullh, 65535469 %add = add nuw nsw i32 %conv10, %shr8470 %conv12 = and i32 %mulhl, 65535471 %add13 = add nuw nsw i32 %conv12, %add472 %shr14 = lshr i32 %add13, 16473 %shr15 = lshr i32 %mullh, 16474 %shr17 = lshr i32 %mulhl, 16475 %add16 = add i32 %shr14, %shr17476 %add18 = add i32 %add16, %shr15477 %add19 = add i32 %mulhh, %add18478 call void (...) @llvm.fake.use(i32 %mullh)479 ret i32 %add19480}481 482define i32 @mul_ladder4_use_conv10(i32 %x, i32 %y) {483; CHECK-LABEL: define i32 @mul_ladder4_use_conv10(484; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {485; CHECK-NEXT: [[ENTRY:.*:]]486; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535487; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16488; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535489; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16490; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]491; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YH]], [[XL]]492; CHECK-NEXT: [[MULHL1:%.*]] = mul nuw i32 [[YL]], [[XH]]493; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]494; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16495; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535496; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV12]], [[SHR8]]497; CHECK-NEXT: [[CONV13:%.*]] = and i32 [[MULHL1]], 65535498; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV13]], [[ADD]]499; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16500; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL]], 16501; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL1]], 16502; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]503; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]504; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]505; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[CONV12]])506; CHECK-NEXT: ret i32 [[ADD19]]507;508entry:509 %xl = and i32 %x, 65535510 %xh = lshr i32 %x, 16511 %yl = and i32 %y, 65535512 %yh = lshr i32 %y, 16513 %mulll = mul nuw i32 %yl, %xl514 %mullh = mul nuw i32 %yh, %xl515 %mulhl = mul nuw i32 %yl, %xh516 %mulhh = mul nuw i32 %yh, %xh517 %shr8 = lshr i32 %mulll, 16518 %conv10 = and i32 %mullh, 65535519 %add = add nuw nsw i32 %conv10, %shr8520 %conv12 = and i32 %mulhl, 65535521 %add13 = add nuw nsw i32 %conv12, %add522 %shr14 = lshr i32 %add13, 16523 %shr15 = lshr i32 %mullh, 16524 %shr17 = lshr i32 %mulhl, 16525 %add16 = add i32 %shr14, %shr17526 %add18 = add i32 %add16, %shr15527 %add19 = add i32 %mulhh, %add18528 call void (...) @llvm.fake.use(i32 %conv10)529 ret i32 %add19530}531