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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes2; RUN: opt -S -passes=argpromotion < %s | FileCheck %s3; Test that we only promote arguments when the caller/callee have compatible4; function attrubtes.5 6target triple = "x86_64-unknown-linux-gnu"7 8; This should promote9define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %arg, ptr readonly %arg1) #0 {10; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer51211; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])12; CHECK-NEXT: bb:13; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]]14; CHECK-NEXT: ret void15;16bb:17 %tmp = load <8 x i64>, ptr %arg118 store <8 x i64> %tmp, ptr %arg19 ret void20}21 22define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %arg) #0 {23; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer51224; CHECK-SAME: (ptr [[ARG:%.*]])25; CHECK-NEXT: bb:26; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 3227; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 3228; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)29; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]]30; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr [[TMP2]], <8 x i64> [[TMP_VAL]])31; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 3232; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 233; CHECK-NEXT: ret void34;35bb:36 %tmp = alloca <8 x i64>, align 3237 %tmp2 = alloca <8 x i64>, align 3238 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)39 call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %tmp2, ptr %tmp)40 %tmp4 = load <8 x i64>, ptr %tmp2, align 3241 store <8 x i64> %tmp4, ptr %arg, align 242 ret void43}44 45; This should promote46define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %arg, ptr readonly %arg1) #1 {47; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer25648; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])49; CHECK-NEXT: bb:50; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]]51; CHECK-NEXT: ret void52;53bb:54 %tmp = load <8 x i64>, ptr %arg155 store <8 x i64> %tmp, ptr %arg56 ret void57}58 59define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %arg) #1 {60; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer25661; CHECK-SAME: (ptr [[ARG:%.*]])62; CHECK-NEXT: bb:63; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 3264; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 3265; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)66; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]]67; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]])68; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 3269; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 270; CHECK-NEXT: ret void71;72bb:73 %tmp = alloca <8 x i64>, align 3274 %tmp2 = alloca <8 x i64>, align 3275 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)76 call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %tmp2, ptr %tmp)77 %tmp4 = load <8 x i64>, ptr %tmp2, align 3278 store <8 x i64> %tmp4, ptr %arg, align 279 ret void80}81 82; This should promote83define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %arg, ptr readonly %arg1) #1 {84; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer25685; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])86; CHECK-NEXT: bb:87; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]]88; CHECK-NEXT: ret void89;90bb:91 %tmp = load <8 x i64>, ptr %arg192 store <8 x i64> %tmp, ptr %arg93 ret void94}95 96define void @avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %arg) #0 {97; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer25698; CHECK-SAME: (ptr [[ARG:%.*]])99; CHECK-NEXT: bb:100; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32101; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32102; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)103; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]]104; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]])105; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32106; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2107; CHECK-NEXT: ret void108;109bb:110 %tmp = alloca <8 x i64>, align 32111 %tmp2 = alloca <8 x i64>, align 32112 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)113 call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %tmp2, ptr %tmp)114 %tmp4 = load <8 x i64>, ptr %tmp2, align 32115 store <8 x i64> %tmp4, ptr %arg, align 2116 ret void117}118 119; This should promote120define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %arg, ptr readonly %arg1) #0 {121; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512122; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])123; CHECK-NEXT: bb:124; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]]125; CHECK-NEXT: ret void126;127bb:128 %tmp = load <8 x i64>, ptr %arg1129 store <8 x i64> %tmp, ptr %arg130 ret void131}132 133define void @avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %arg) #1 {134; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512135; CHECK-SAME: (ptr [[ARG:%.*]])136; CHECK-NEXT: bb:137; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32138; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32139; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)140; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]]141; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr [[TMP2]], <8 x i64> [[TMP_VAL]])142; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32143; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2144; CHECK-NEXT: ret void145;146bb:147 %tmp = alloca <8 x i64>, align 32148 %tmp2 = alloca <8 x i64>, align 32149 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)150 call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %tmp2, ptr %tmp)151 %tmp4 = load <8 x i64>, ptr %tmp2, align 32152 store <8 x i64> %tmp4, ptr %arg, align 2153 ret void154}155 156; This should not promote157define internal fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %arg, ptr readonly %arg1) #1 {158; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256159; CHECK-SAME: (ptr [[ARG:%.*]], ptr readonly [[ARG1:%.*]])160; CHECK-NEXT: bb:161; CHECK-NEXT: [[TMP:%.*]] = load <8 x i64>, ptr [[ARG1]]162; CHECK-NEXT: store <8 x i64> [[TMP]], ptr [[ARG]]163; CHECK-NEXT: ret void164;165bb:166 %tmp = load <8 x i64>, ptr %arg1167 store <8 x i64> %tmp, ptr %arg168 ret void169}170 171define void @avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %arg) #2 {172; CHECK-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256173; CHECK-SAME: (ptr [[ARG:%.*]])174; CHECK-NEXT: bb:175; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32176; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32177; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)178; CHECK-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr [[TMP2]], ptr [[TMP]])179; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32180; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2181; CHECK-NEXT: ret void182;183bb:184 %tmp = alloca <8 x i64>, align 32185 %tmp2 = alloca <8 x i64>, align 32186 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)187 call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %tmp2, ptr %tmp)188 %tmp4 = load <8 x i64>, ptr %tmp2, align 32189 store <8 x i64> %tmp4, ptr %arg, align 2190 ret void191}192 193; This should not promote194define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %arg, ptr readonly %arg1) #2 {195; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256196; CHECK-SAME: (ptr [[ARG:%.*]], ptr readonly [[ARG1:%.*]])197; CHECK-NEXT: bb:198; CHECK-NEXT: [[TMP:%.*]] = load <8 x i64>, ptr [[ARG1]]199; CHECK-NEXT: store <8 x i64> [[TMP]], ptr [[ARG]]200; CHECK-NEXT: ret void201;202bb:203 %tmp = load <8 x i64>, ptr %arg1204 store <8 x i64> %tmp, ptr %arg205 ret void206}207 208define void @avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %arg) #1 {209; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256210; CHECK-SAME: (ptr [[ARG:%.*]])211; CHECK-NEXT: bb:212; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32213; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32214; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)215; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr [[TMP2]], ptr [[TMP]])216; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32217; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2218; CHECK-NEXT: ret void219;220bb:221 %tmp = alloca <8 x i64>, align 32222 %tmp2 = alloca <8 x i64>, align 32223 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)224 call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %tmp2, ptr %tmp)225 %tmp4 = load <8 x i64>, ptr %tmp2, align 32226 store <8 x i64> %tmp4, ptr %arg, align 2227 ret void228}229 230; This should promote231define internal fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %arg, ptr readonly %arg1) #3 {232; CHECK-LABEL: define {{[^@]+}}@callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256233; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])234; CHECK-NEXT: bb:235; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]]236; CHECK-NEXT: ret void237;238bb:239 %tmp = load <8 x i64>, ptr %arg1240 store <8 x i64> %tmp, ptr %arg241 ret void242}243 244define void @avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %arg) #4 {245; CHECK-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256246; CHECK-SAME: (ptr [[ARG:%.*]])247; CHECK-NEXT: bb:248; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32249; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32250; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)251; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]]252; CHECK-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]])253; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32254; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2255; CHECK-NEXT: ret void256;257bb:258 %tmp = alloca <8 x i64>, align 32259 %tmp2 = alloca <8 x i64>, align 32260 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)261 call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %tmp2, ptr %tmp)262 %tmp4 = load <8 x i64>, ptr %tmp2, align 32263 store <8 x i64> %tmp4, ptr %arg, align 2264 ret void265}266 267; This should promote268define internal fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %arg, ptr readonly %arg1) #4 {269; CHECK-LABEL: define {{[^@]+}}@callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256270; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]])271; CHECK-NEXT: bb:272; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]]273; CHECK-NEXT: ret void274;275bb:276 %tmp = load <8 x i64>, ptr %arg1277 store <8 x i64> %tmp, ptr %arg278 ret void279}280 281define void @avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %arg) #3 {282; CHECK-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256283; CHECK-SAME: (ptr [[ARG:%.*]])284; CHECK-NEXT: bb:285; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32286; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32287; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)288; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]]289; CHECK-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]])290; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32291; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2292; CHECK-NEXT: ret void293;294bb:295 %tmp = alloca <8 x i64>, align 32296 %tmp2 = alloca <8 x i64>, align 32297 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)298 call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %tmp2, ptr %tmp)299 %tmp4 = load <8 x i64>, ptr %tmp2, align 32300 store <8 x i64> %tmp4, ptr %arg, align 2301 ret void302}303 304; If the arguments are scalar, its ok to promote.305define internal i32 @scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %X, ptr %Y) #2 {306; CHECK-LABEL: define {{[^@]+}}@scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256307; CHECK-SAME: (i32 [[X_VAL:%.*]], i32 [[Y_VAL:%.*]])308; CHECK-NEXT: [[C:%.*]] = add i32 [[X_VAL]], [[Y_VAL]]309; CHECK-NEXT: ret i32 [[C]]310;311 %A = load i32, ptr %X312 %B = load i32, ptr %Y313 %C = add i32 %A, %B314 ret i32 %C315}316 317define i32 @scalar_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %B) #2 {318; CHECK-LABEL: define {{[^@]+}}@scalar_avx512_legal256_prefer256_call_avx512_legal512_prefer256319; CHECK-SAME: (ptr [[B:%.*]])320; CHECK-NEXT: [[A:%.*]] = alloca i32321; CHECK-NEXT: store i32 1, ptr [[A]]322; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]]323; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]]324; CHECK-NEXT: [[C:%.*]] = call i32 @scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(i32 [[A_VAL]], i32 [[B_VAL]])325; CHECK-NEXT: ret i32 [[C]]326;327 %A = alloca i32328 store i32 1, ptr %A329 %C = call i32 @scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %A, ptr %B)330 ret i32 %C331}332 333; If the arguments are scalar, its ok to promote.334define internal i32 @scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %X, ptr %Y) #2 {335; CHECK-LABEL: define {{[^@]+}}@scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256336; CHECK-SAME: (i32 [[X_VAL:%.*]], i32 [[Y_VAL:%.*]])337; CHECK-NEXT: [[C:%.*]] = add i32 [[X_VAL]], [[Y_VAL]]338; CHECK-NEXT: ret i32 [[C]]339;340 %A = load i32, ptr %X341 %B = load i32, ptr %Y342 %C = add i32 %A, %B343 ret i32 %C344}345 346define i32 @scalar_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %B) #2 {347; CHECK-LABEL: define {{[^@]+}}@scalar_avx512_legal512_prefer256_call_avx512_legal256_prefer256348; CHECK-SAME: (ptr [[B:%.*]])349; CHECK-NEXT: [[A:%.*]] = alloca i32350; CHECK-NEXT: store i32 1, ptr [[A]]351; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]]352; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]]353; CHECK-NEXT: [[C:%.*]] = call i32 @scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(i32 [[A_VAL]], i32 [[B_VAL]])354; CHECK-NEXT: ret i32 [[C]]355;356 %A = alloca i32357 store i32 1, ptr %A358 %C = call i32 @scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %A, ptr %B)359 ret i32 %C360}361 362; Function Attrs: argmemonly nounwind363declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #5364 365attributes #0 = { inlinehint norecurse nounwind uwtable "target-features"="+avx512vl" "min-legal-vector-width"="512" "prefer-vector-width"="512" }366attributes #1 = { inlinehint norecurse nounwind uwtable "target-features"="+avx512vl" "min-legal-vector-width"="512" "prefer-vector-width"="256" }367attributes #2 = { inlinehint norecurse nounwind uwtable "target-features"="+avx512vl" "min-legal-vector-width"="256" "prefer-vector-width"="256" }368attributes #3 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" "min-legal-vector-width"="512" "prefer-vector-width"="256" }369attributes #4 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" "min-legal-vector-width"="256" "prefer-vector-width"="256" }370attributes #5 = { argmemonly nounwind }371