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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=atomic-expand %s | FileCheck -check-prefix=GFX90A %s3 4declare i32 @llvm.amdgcn.workitem.id.x()5 6define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, float %in) #0 {7; GFX90A-LABEL: @divergent_cfg(8; GFX90A-NEXT: entry:9; GFX90A-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()10; GFX90A-NEXT: [[D_CMP:%.*]] = icmp ult i32 [[TID]], 1611; GFX90A-NEXT: br i1 [[D_CMP]], label [[IF:%.*]], label [[ELSE:%.*]]12; GFX90A: if:13; GFX90A-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(1) [[OUT:%.*]], align 414; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]15; GFX90A: atomicrmw.start:16; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP0]], [[IF]] ], [ [[TMP4:%.*]], [[ATOMICRMW_START]] ]17; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[IN:%.*]]18; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float [[NEW]] to i3219; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float [[LOADED]] to i3220; GFX90A-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(1) [[OUT]], i32 [[TMP2]], i32 [[TMP1]] seq_cst seq_cst, align 421; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 122; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP3]], 023; GFX90A-NEXT: [[TMP4]] = bitcast i32 [[NEWLOADED]] to float24; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]25; GFX90A: atomicrmw.end:26; GFX90A-NEXT: br label [[ENDIF:%.*]]27; GFX90A: else:28; GFX90A-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(1) [[OUT]], align 429; GFX90A-NEXT: br label [[ATOMICRMW_START2:%.*]]30; GFX90A: atomicrmw.start2:31; GFX90A-NEXT: [[LOADED3:%.*]] = phi float [ [[TMP5]], [[ELSE]] ], [ [[TMP9:%.*]], [[ATOMICRMW_START2]] ]32; GFX90A-NEXT: [[NEW4:%.*]] = fadd float [[LOADED3]], [[IN]]33; GFX90A-NEXT: [[TMP6:%.*]] = bitcast float [[NEW4]] to i3234; GFX90A-NEXT: [[TMP7:%.*]] = bitcast float [[LOADED3]] to i3235; GFX90A-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[OUT]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 436; GFX90A-NEXT: [[SUCCESS5:%.*]] = extractvalue { i32, i1 } [[TMP8]], 137; GFX90A-NEXT: [[NEWLOADED6:%.*]] = extractvalue { i32, i1 } [[TMP8]], 038; GFX90A-NEXT: [[TMP9]] = bitcast i32 [[NEWLOADED6]] to float39; GFX90A-NEXT: br i1 [[SUCCESS5]], label [[ATOMICRMW_END1:%.*]], label [[ATOMICRMW_START2]]40; GFX90A: atomicrmw.end1:41; GFX90A-NEXT: br label [[ENDIF]]42; GFX90A: endif:43; GFX90A-NEXT: [[COMBINE:%.*]] = phi float [ [[TMP4]], [[ATOMICRMW_END]] ], [ [[TMP9]], [[ATOMICRMW_END1]] ]44; GFX90A-NEXT: store float [[COMBINE]], ptr addrspace(1) [[OUT]], align 445; GFX90A-NEXT: ret void46;47entry:48 %tid = call i32 @llvm.amdgcn.workitem.id.x()49 %d_cmp = icmp ult i32 %tid, 1650 br i1 %d_cmp, label %if, label %else51 52if:53 %res_if = atomicrmw fadd ptr addrspace(1) %out, float %in seq_cst54 br label %endif55 56else:57 %res_else = atomicrmw fadd ptr addrspace(1) %out, float %in seq_cst58 br label %endif59 60endif:61 %combine = phi float [%res_if, %if], [%res_else, %else]62 store float %combine, ptr addrspace(1) %out63 ret void64}65 66attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }67