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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=hexagon-- -passes=atomic-expand %s | FileCheck %s3 4define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {5; CHECK-LABEL: @test_atomicrmw_fadd_f32(6; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]7; CHECK: atomicrmw.start:8; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(ptr [[PTR:%.*]])9; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[LARX]] to float10; CHECK-NEXT: [[NEW:%.*]] = fadd float [[TMP1]], [[VALUE:%.*]]11; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[NEW]] to i3212; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(ptr [[PTR]], i32 [[TMP2]])13; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[STCX]], 014; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i3215; CHECK-NEXT: br i1 [[TMP3]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]16; CHECK: atomicrmw.end:17; CHECK-NEXT: ret float [[TMP1]]18;19 %res = atomicrmw fadd ptr %ptr, float %value seq_cst20 ret float %res21}22 23define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {24; CHECK-LABEL: @test_atomicrmw_fsub_f32(25; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]26; CHECK: atomicrmw.start:27; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(ptr [[PTR:%.*]])28; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[LARX]] to float29; CHECK-NEXT: [[NEW:%.*]] = fsub float [[TMP1]], [[VALUE:%.*]]30; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[NEW]] to i3231; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(ptr [[PTR]], i32 [[TMP2]])32; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[STCX]], 033; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i3234; CHECK-NEXT: br i1 [[TMP3]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]35; CHECK: atomicrmw.end:36; CHECK-NEXT: ret float [[TMP1]]37;38 %res = atomicrmw fsub ptr %ptr, float %value seq_cst39 ret float %res40}41 42