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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=bdce < %s | FileCheck %s3define i32 @ZEXT_0(i16 %a) {4; CHECK-LABEL: @ZEXT_0(5; CHECK-NEXT: entry:6; CHECK-NEXT: [[EXT1:%.*]] = zext i16 [[A:%.*]] to i327; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT1]], 652808; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT1]], 89; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 25510; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]]11; CHECK-NEXT: ret i32 [[OR]]12;13entry:14 %ext = sext i16 %a to i3215 %and = and i32 %ext, 6528016 %lsr = lshr i32 %ext, 817 %and2 = and i32 %lsr, 25518 %or = or i32 %and, %and219 ret i32 %or20}21 22define i32 @ZEXT_1(i16 %a) {23; CHECK-LABEL: @ZEXT_1(24; CHECK-NEXT: entry:25; CHECK-NEXT: [[EXT1:%.*]] = zext i16 [[A:%.*]] to i3226; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT1]], 827; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 25528; CHECK-NEXT: [[AND:%.*]] = or i32 [[EXT1]], -6553629; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]]30; CHECK-NEXT: ret i32 [[OR]]31;32entry:33 %ext = sext i16 %a to i3234 %lsr = lshr i32 %ext, 835 %and2 = and i32 %lsr, 25536 %and = or i32 %ext, 429490176037 %or = or i32 %and, %and238 ret i32 %or39}40 41define i16 @NOT_ZEXT_0(i16 %a) {42; CHECK-LABEL: @NOT_ZEXT_0(43; CHECK-NEXT: entry:44; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[A:%.*]] to i3245; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT]], 6528046; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 947; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 25548; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]]49; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[OR]] to i1650; CHECK-NEXT: ret i16 [[RET]]51;52entry:53 %ext = sext i16 %a to i3254 %and = and i32 %ext, 6528055 %lsr = lshr i32 %ext, 956 %and2 = and i32 %lsr, 25557 %or = or i32 %and, %and258 %ret = trunc i32 %or to i1659 ret i16 %ret60}61 62define i32 @NOT_ZEXT_1(i16 %a) {63; CHECK-LABEL: @NOT_ZEXT_1(64; CHECK-NEXT: entry:65; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[A:%.*]] to i3266; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT]], 8528067; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 868; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 25569; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]]70; CHECK-NEXT: ret i32 [[OR]]71;72entry:73 %ext = sext i16 %a to i3274 %and = and i32 %ext, 8528075 %lsr = lshr i32 %ext, 876 %and2 = and i32 %lsr, 25577 %or = or i32 %and, %and278 ret i32 %or79}80 81define i32 @NOT_ZEXT_2(i16 %a) {82; CHECK-LABEL: @NOT_ZEXT_2(83; CHECK-NEXT: entry:84; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[A:%.*]] to i3285; CHECK-NEXT: [[LSR:%.*]] = lshr i32 [[EXT]], 886; CHECK-NEXT: [[AND2:%.*]] = and i32 [[LSR]], 25587; CHECK-NEXT: [[AND:%.*]] = xor i32 [[EXT]], -6553688; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND2]]89; CHECK-NEXT: ret i32 [[OR]]90;91entry:92 %ext = sext i16 %a to i3293 %lsr = lshr i32 %ext, 894 %and2 = and i32 %lsr, 25595 %and = xor i32 %ext, 429490176096 %or = or i32 %and, %and297 ret i32 %or98}99 100define i16 @clear_assumptions(i8 %x, i16 %y) {101; CHECK-LABEL: @clear_assumptions(102; CHECK-NEXT: [[EXT1:%.*]] = zext i8 [[X:%.*]] to i16103; CHECK-NEXT: [[ADD:%.*]] = add i16 [[EXT1]], [[Y:%.*]]104; CHECK-NEXT: [[AND:%.*]] = and i16 [[ADD]], 255105; CHECK-NEXT: ret i16 [[AND]]106;107 %ext = sext i8 %x to i16108 %add = add nsw i16 %ext, %y109 %and = and i16 %add, 255110 ret i16 %and111}112