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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -S < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define void @do_not_sink_scalable_vector_compare(ptr %a, ptr %b) #0 {7; CHECK-LABEL: define void @do_not_sink_scalable_vector_compare(8; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: [[ENTRY:.*]]:10; CHECK-NEXT: [[STEP_VECTOR:%.*]] = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()11; CHECK-NEXT: [[TMP0:%.*]] = icmp ult <vscale x 4 x i32> [[STEP_VECTOR]], splat (i32 16)12; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]13; CHECK: [[VECTOR_BODY]]:14; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]15; CHECK-NEXT: [[SRC:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[INDEX]]16; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[SRC]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> poison)17; CHECK-NEXT: [[DST:%.*]] = getelementptr inbounds ptr, ptr [[B]], i64 [[INDEX]]18; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[WIDE_LOAD]], ptr align 4 [[DST]], <vscale x 4 x i1> [[TMP0]])19; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1620; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[INDEX_NEXT]], 102421; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[VECTOR_END:.*]], label %[[VECTOR_BODY]]22; CHECK: [[VECTOR_END]]:23; CHECK-NEXT: ret void24;25entry:26 %step.vector = call <vscale x 4 x i32> @llvm.stepvector()27 %mask = icmp ult <vscale x 4 x i32> %step.vector, splat (i32 16)28 br label %vector.body29 30vector.body:31 %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]32 %src = getelementptr inbounds ptr, ptr %a, i64 %index33 %wide.load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %src, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)34 %dst = getelementptr inbounds ptr, ptr %b, i64 %index35 call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %wide.load, ptr %dst, i32 4, <vscale x 4 x i1> %mask)36 %index.next = add nuw i64 %index, 1637 %exit.cond = icmp eq i64 %index.next, 102438 br i1 %exit.cond, label %vector.end, label %vector.body39 40vector.end:41 ret void42}43 44attributes #0 = { "target-features"="+sve" }45