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1; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' < %s | FileCheck %s2 3target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"4target triple = "nvptx64-nvidia-cuda"5 6; We only use the div instruction -- the rem should be DCE'ed.7; CHECK-LABEL: @div_only8define void @div_only(i64 %a, i64 %b, ptr %retptr) {9 ; CHECK: udiv i3210 ; CHECK-NOT: urem11 ; CHECK: sdiv i6412 ; CHECK-NOT: rem13 %d = sdiv i64 %a, %b14 store i64 %d, ptr %retptr15 ret void16}17 18; We only use the rem instruction -- the div should be DCE'ed.19; CHECK-LABEL: @rem_only20define void @rem_only(i64 %a, i64 %b, ptr %retptr) {21 ; CHECK-NOT: div22 ; CHECK: urem i3223 ; CHECK-NOT: div24 ; CHECK: rem i6425 ; CHECK-NOT: div26 %d = srem i64 %a, %b27 store i64 %d, ptr %retptr28 ret void29}30 31; CHECK-LABEL: @udiv_by_constant(32define i64 @udiv_by_constant(i32 %a) {33; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i6434; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i3235; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 5036; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i6437; CHECK-NEXT: ret i64 [[TMP3]]38 39 %a.zext = zext i32 %a to i6440 %wide.div = udiv i64 %a.zext, 5041 ret i64 %wide.div42}43 44; CHECK-LABEL: @urem_by_constant(45define i64 @urem_by_constant(i32 %a) {46; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i6447; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i3248; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[TMP1]], 5049; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i6450; CHECK-NEXT: ret i64 [[TMP3]]51 52 %a.zext = zext i32 %a to i6453 %wide.div = urem i64 %a.zext, 5054 ret i64 %wide.div55}56 57; Negative test: instead of emitting a runtime check on %a, we prefer to let the58; DAGCombiner transform this division by constant into a multiplication (with a59; "magic constant").60;61; CHECK-LABEL: @udiv_by_constant_negative_0(62define i64 @udiv_by_constant_negative_0(i64 %a) {63; CHECK-NEXT: [[WIDE_DIV:%.*]] = udiv i64 [[A:%.*]], 5064; CHECK-NEXT: ret i64 [[WIDE_DIV]]65 66 %wide.div = udiv i64 %a, 5067 ret i64 %wide.div68}69 70; Negative test: while we know the dividend is short, the divisor isn't. This71; test is here for completeness, but instcombine will optimize this to return 0.72;73; CHECK-LABEL: @udiv_by_constant_negative_1(74define i64 @udiv_by_constant_negative_1(i32 %a) {75; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i6476; CHECK-NEXT: [[WIDE_DIV:%.*]] = udiv i64 [[A_ZEXT]], 858993459277; CHECK-NEXT: ret i64 [[WIDE_DIV]]78 79 %a.zext = zext i32 %a to i6480 %wide.div = udiv i64 %a.zext, 8589934592 ;; == 1 << 3381 ret i64 %wide.div82}83 84; URem version of udiv_by_constant_negative_085;86; CHECK-LABEL: @urem_by_constant_negative_0(87define i64 @urem_by_constant_negative_0(i64 %a) {88; CHECK-NEXT: [[WIDE_DIV:%.*]] = urem i64 [[A:%.*]], 5089; CHECK-NEXT: ret i64 [[WIDE_DIV]]90 91 %wide.div = urem i64 %a, 5092 ret i64 %wide.div93}94 95; URem version of udiv_by_constant_negative_196;97; CHECK-LABEL: @urem_by_constant_negative_1(98define i64 @urem_by_constant_negative_1(i32 %a) {99; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64100; CHECK-NEXT: [[WIDE_DIV:%.*]] = urem i64 [[A_ZEXT]], 8589934592101; CHECK-NEXT: ret i64 [[WIDE_DIV]]102 103 %a.zext = zext i32 %a to i64104 %wide.div = urem i64 %a.zext, 8589934592 ;; == 1 << 33105 ret i64 %wide.div106}107