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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' %s | FileCheck %s3 4target triple = "x86_64-unknown-linux"5 6declare i1 @cond(float)7 8define void @scaled_reg_does_not_dominate_insert_point(ptr %src) {9; CHECK-LABEL: define void @scaled_reg_does_not_dominate_insert_point(10; CHECK-SAME: ptr [[SRC:%.*]]) {11; CHECK-NEXT: [[BB:.*]]:12; CHECK-NEXT: br label %[[LOOP:.*]]13; CHECK: [[LOOP]]:14; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[BB]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]15; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 116; CHECK-NEXT: [[SUNKADDR2:%.*]] = mul i64 [[IV_NEXT]], 217; CHECK-NEXT: [[SUNKADDR3:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[SUNKADDR2]]18; CHECK-NEXT: [[SUNKADDR4:%.*]] = getelementptr i8, ptr [[SUNKADDR3]], i64 619; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[SUNKADDR4]], align 420; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV]], 221; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[SUNKADDR]]22; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[SUNKADDR1]], align 423; CHECK-NEXT: [[TMP0:%.*]] = call i1 @cond(float [[L_0]])24; CHECK-NEXT: [[C:%.*]] = call i1 @cond(float [[L_1]])25; CHECK-NEXT: br i1 [[C]], label %[[LOOP]], label %[[EXIT:.*]]26; CHECK: [[EXIT]]:27; CHECK-NEXT: ret void28;29bb:30 %gep.base = getelementptr i8, ptr %src, i64 831 br label %loop32 33loop:34 %iv = phi i64 [ 0, %bb ], [ %iv.next, %loop ]35 %iv.shl = shl i64 %iv, 136 %gep.shl = getelementptr i8, ptr %gep.base, i64 %iv.shl37 %gep.sub = getelementptr i8, ptr %gep.shl, i64 -838 %iv.next = add i64 %iv, 139 %l.0 = load float, ptr %gep.shl, align 440 %l.1 = load float, ptr %gep.sub, align 441 call i1 @cond(float %l.0)42 %c = call i1 @cond(float %l.1)43 br i1 %c, label %loop, label %exit44 45exit:46 ret void47}48 49define void @check_dt_after_modifying_cfg(ptr %dst, i64 %x, i8 %y, i8 %z) {50; CHECK-LABEL: define void @check_dt_after_modifying_cfg(51; CHECK-SAME: ptr [[DST:%.*]], i64 [[X:%.*]], i8 [[Y:%.*]], i8 [[Z:%.*]]) {52; CHECK-NEXT: [[ENTRY:.*]]:53; CHECK-NEXT: [[OFFSET:%.*]] = lshr i64 [[X]], 254; CHECK-NEXT: [[SEL_FROZEN:%.*]] = freeze i8 [[Z]]55; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[SEL_FROZEN]], 056; CHECK-NEXT: br i1 [[CMP]], label %[[SELECT_END:.*]], label %[[SELECT_FALSE_SINK:.*]]57; CHECK: [[SELECT_FALSE_SINK]]:58; CHECK-NEXT: [[SMIN:%.*]] = tail call i8 @llvm.smin.i8(i8 [[Y]], i8 0)59; CHECK-NEXT: br label %[[SELECT_END]]60; CHECK: [[SELECT_END]]:61; CHECK-NEXT: [[SEL:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[SMIN]], %[[SELECT_FALSE_SINK]] ]62; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET]]63; CHECK-NEXT: store i8 [[SEL]], ptr [[SUNKADDR]], align 164; CHECK-NEXT: ret void65;66entry:67 %offset = lshr i64 %x, 268 %gep.dst = getelementptr i8, ptr %dst, i64 %offset69 %smin = tail call i8 @llvm.smin.i8(i8 %y, i8 0)70 %cmp = icmp slt i8 %z, 071 %sel = select i1 %cmp, i8 0, i8 %smin72 store i8 %sel, ptr %gep.dst, align 173 ret void74}75 76declare i8 @llvm.smin.i8(i8, i8) #077