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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt -mtriple=arm64-darwin-unknown -S -passes=consthoist < %s | FileCheck %s3; RUN: opt -mtriple=arm64-darwin-unknown -S -passes=consthoist -use-constant-int-for-fixed-length-splat -use-constant-int-for-scalable-splat < %s | FileCheck %s4 5define i128 @test1(i128 %a) {6; CHECK-LABEL: define i128 @test1(7; CHECK-SAME: i128 [[A:%.*]]) {8; CHECK-NEXT: [[CONST:%.*]] = bitcast i128 12297829382473034410122878 to i1289; CHECK-NEXT: [[TMP1:%.*]] = add i128 [[A]], [[CONST]]10; CHECK-NEXT: [[TMP2:%.*]] = add i128 [[TMP1]], [[CONST]]11; CHECK-NEXT: ret i128 [[TMP2]]12;13 %1 = add i128 %a, 1229782938247303441012287814 %2 = add i128 %1, 1229782938247303441012287815 ret i128 %216}17 18; Check that we don't hoist large, but cheap constants19define i512 @test2(i512 %a) {20; CHECK-LABEL: define i512 @test2(21; CHECK-SAME: i512 [[A:%.*]]) {22; CHECK-NEXT: [[TMP1:%.*]] = and i512 [[A]], 723; CHECK-NEXT: [[TMP2:%.*]] = or i512 [[TMP1]], 724; CHECK-NEXT: ret i512 [[TMP2]]25;26 %1 = and i512 %a, 727 %2 = or i512 %1, 728 ret i512 %229}30 31; Check that we don't hoist the shift value of a shift instruction.32define i512 @test3(i512 %a) {33; CHECK-LABEL: define i512 @test3(34; CHECK-SAME: i512 [[A:%.*]]) {35; CHECK-NEXT: [[TMP1:%.*]] = shl i512 [[A]], 50436; CHECK-NEXT: [[TMP2:%.*]] = ashr i512 [[TMP1]], 50437; CHECK-NEXT: ret i512 [[TMP2]]38;39 %1 = shl i512 %a, 50440 %2 = ashr i512 %1, 50441 ret i512 %242}43 44; Ensure the code generator has the information necessary to simply sdiv.45define i64 @sdiv(i64 %a) {46; CHECK-LABEL: define i64 @sdiv(47; CHECK-SAME: i64 [[A:%.*]]) {48; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[A]], 429496708749; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 429496708750; CHECK-NEXT: ret i64 [[TMP2]]51;52 %1 = sdiv i64 %a, 429496708753 %2 = add i64 %1, 429496708754 ret i64 %255}56 57; Ensure the code generator has the information necessary to simply srem.58define i64 @srem(i64 %a) {59; CHECK-LABEL: define i64 @srem(60; CHECK-SAME: i64 [[A:%.*]]) {61; CHECK-NEXT: [[TMP1:%.*]] = srem i64 [[A]], 429496708762; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 429496708763; CHECK-NEXT: ret i64 [[TMP2]]64;65 %1 = srem i64 %a, 429496708766 %2 = add i64 %1, 429496708767 ret i64 %268}69 70; Ensure the code generator has the information necessary to simply udiv.71define i64 @udiv(i64 %a) {72; CHECK-LABEL: define i64 @udiv(73; CHECK-SAME: i64 [[A:%.*]]) {74; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[A]], 429496708775; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 429496708776; CHECK-NEXT: ret i64 [[TMP2]]77;78 %1 = udiv i64 %a, 429496708779 %2 = add i64 %1, 429496708780 ret i64 %281}82 83; Ensure the code generator has the information necessary to simply urem.84define i64 @urem(i64 %a) {85; CHECK-LABEL: define i64 @urem(86; CHECK-SAME: i64 [[A:%.*]]) {87; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[A]], 429496708788; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 429496708789; CHECK-NEXT: ret i64 [[TMP2]]90;91 %1 = urem i64 %a, 429496708792 %2 = add i64 %1, 429496708793 ret i64 %294}95 96; Code generator will not decompose divide like operations when the divisor is97; no a constant.98define i64 @sdiv_non_const_divisor(i64 %a) {99; CHECK-LABEL: define i64 @sdiv_non_const_divisor(100; CHECK-SAME: i64 [[A:%.*]]) {101; CHECK-NEXT: [[CONST:%.*]] = bitcast i64 4294967087 to i64102; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[CONST]], [[A]]103; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]104; CHECK-NEXT: ret i64 [[TMP2]]105;106 %1 = sdiv i64 4294967087, %a107 %2 = add i64 %1, 4294967087108 ret i64 %2109}110 111; Code generator emits divide instructions when optimising for size.112define i64 @sdiv_minsize(i64 %a) minsize {113; CHECK-LABEL: define i64 @sdiv_minsize(114; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] {115; CHECK-NEXT: [[CONST:%.*]] = bitcast i64 4294967087 to i64116; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[A]], [[CONST]]117; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]118; CHECK-NEXT: ret i64 [[TMP2]]119;120 %1 = sdiv i64 %a, 4294967087121 %2 = add i64 %1, 4294967087122 ret i64 %2123}124 125define <2 x i64> @sdiv_v2i64(<2 x i64> %a) {126; CHECK-LABEL: define <2 x i64> @sdiv_v2i64(127; CHECK-SAME: <2 x i64> [[A:%.*]]) {128; CHECK-NEXT: [[TMP1:%.*]] = sdiv <2 x i64> [[A]], splat (i64 4294967087)129; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i64> [[TMP1]], splat (i64 4294967087)130; CHECK-NEXT: ret <2 x i64> [[TMP2]]131;132 %1 = sdiv <2 x i64> %a, <i64 4294967087, i64 4294967087>133 %2 = add <2 x i64> %1, <i64 4294967087, i64 4294967087>134 ret <2 x i64> %2135}136 137define <vscale x 2 x i64> @sdiv_nxv2i64(<vscale x 2 x i64> %a) {138; CHECK-LABEL: define <vscale x 2 x i64> @sdiv_nxv2i64(139; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]]) {140; CHECK-NEXT: [[TMP1:%.*]] = sdiv <vscale x 2 x i64> [[A]], splat (i64 4294967087)141; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 2 x i64> [[TMP1]], splat (i64 4294967087)142; CHECK-NEXT: ret <vscale x 2 x i64> [[TMP2]]143;144 %1 = sdiv <vscale x 2 x i64> %a, splat (i64 4294967087)145 %2 = add <vscale x 2 x i64> %1, splat (i64 4294967087)146 ret <vscale x 2 x i64> %2147}148