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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s3 4declare void @use(i1)5declare void @llvm.assume(i1)6 7define void @test.not.uge.ult(i8 %start, i8 %high) {8; CHECK-LABEL: @test.not.uge.ult(9; CHECK-NEXT: entry:10; CHECK-NEXT: [[ADD_PTR_I:%.*]] = add nsw i8 [[START:%.*]], 311; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[ADD_PTR_I]], [[HIGH:%.*]]12; CHECK-NEXT: br i1 [[C_1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]13; CHECK: if.then:14; CHECK-NEXT: ret void15; CHECK: if.end:16; CHECK-NEXT: [[T_0:%.*]] = icmp ult i8 [[START]], [[HIGH]]17; CHECK-NEXT: call void @use(i1 [[T_0]])18; CHECK-NEXT: [[START_1:%.*]] = add nsw i8 [[START]], 119; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[START_1]], [[HIGH]]20; CHECK-NEXT: call void @use(i1 [[T_1]])21; CHECK-NEXT: [[START_2:%.*]] = add nsw i8 [[START]], 222; CHECK-NEXT: [[T_2:%.*]] = icmp ult i8 [[START_2]], [[HIGH]]23; CHECK-NEXT: call void @use(i1 [[T_2]])24; CHECK-NEXT: [[START_3:%.*]] = add nsw i8 [[START]], 325; CHECK-NEXT: [[T_3:%.*]] = icmp ult i8 [[START_3]], [[HIGH]]26; CHECK-NEXT: call void @use(i1 [[T_3]])27; CHECK-NEXT: [[START_4:%.*]] = add nsw i8 [[START]], 428; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8 [[START_4]], [[HIGH]]29; CHECK-NEXT: call void @use(i1 [[C_4]])30; CHECK-NEXT: ret void31;32entry:33 %add.ptr.i = add nsw i8 %start, 334 %c.1 = icmp uge i8 %add.ptr.i, %high35 br i1 %c.1, label %if.then, label %if.end36 37if.then: ; preds = %entry38 ret void39 40if.end: ; preds = %entry41 %t.0 = icmp ult i8 %start, %high42 call void @use(i1 %t.0)43 %start.1 = add nsw i8 %start, 144 %t.1 = icmp ult i8 %start.1, %high45 call void @use(i1 %t.1)46 %start.2 = add nsw i8 %start, 247 %t.2 = icmp ult i8 %start.2, %high48 call void @use(i1 %t.2)49 %start.3 = add nsw i8 %start, 350 %t.3 = icmp ult i8 %start.3, %high51 call void @use(i1 %t.3)52 %start.4 = add nsw i8 %start, 453 %c.4 = icmp ult i8 %start.4, %high54 call void @use(i1 %c.4)55 ret void56}57 58define void @test.not.sge.slt(i8 %start, i8 %high) {59; CHECK-LABEL: @test.not.sge.slt(60; CHECK-NEXT: entry:61; CHECK-NEXT: [[ADD_PTR_I:%.*]] = add nsw i8 [[START:%.*]], 362; CHECK-NEXT: [[C_1:%.*]] = icmp sge i8 [[ADD_PTR_I]], [[HIGH:%.*]]63; CHECK-NEXT: br i1 [[C_1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]64; CHECK: if.then:65; CHECK-NEXT: ret void66; CHECK: if.end:67; CHECK-NEXT: call void @use(i1 true)68; CHECK-NEXT: [[START_1:%.*]] = add nsw i8 [[START]], 169; CHECK-NEXT: call void @use(i1 true)70; CHECK-NEXT: [[START_2:%.*]] = add nsw i8 [[START]], 271; CHECK-NEXT: call void @use(i1 true)72; CHECK-NEXT: [[START_3:%.*]] = add nsw i8 [[START]], 373; CHECK-NEXT: call void @use(i1 true)74; CHECK-NEXT: [[START_4:%.*]] = add nsw i8 [[START]], 475; CHECK-NEXT: [[C_4:%.*]] = icmp slt i8 [[START_4]], [[HIGH]]76; CHECK-NEXT: call void @use(i1 [[C_4]])77; CHECK-NEXT: ret void78;79entry:80 %add.ptr.i = add nsw i8 %start, 381 %c.1 = icmp sge i8 %add.ptr.i, %high82 br i1 %c.1, label %if.then, label %if.end83 84if.then: ; preds = %entry85 ret void86 87if.end: ; preds = %entry88 %t.0 = icmp slt i8 %start, %high89 call void @use(i1 %t.0)90 %start.1 = add nsw i8 %start, 191 %t.1 = icmp slt i8 %start.1, %high92 call void @use(i1 %t.1)93 %start.2 = add nsw i8 %start, 294 %t.2 = icmp slt i8 %start.2, %high95 call void @use(i1 %t.2)96 %start.3 = add nsw i8 %start, 397 %t.3 = icmp slt i8 %start.3, %high98 call void @use(i1 %t.3)99 %start.4 = add nsw i8 %start, 4100 %c.4 = icmp slt i8 %start.4, %high101 call void @use(i1 %c.4)102 ret void103}104 105define void @test.decompose.nonconst(i8 %a, i8 %b, i8 %c, i8 %d) {106; CHECK-LABEL: @test.decompose.nonconst(107; CHECK-NEXT: entry:108; CHECK-NEXT: [[C_0:%.*]] = icmp sge i8 [[A:%.*]], [[C:%.*]]109; CHECK-NEXT: [[C_1:%.*]] = icmp sge i8 [[B:%.*]], [[C]]110; CHECK-NEXT: [[AND_0:%.*]] = and i1 [[C_0]], [[C_1]]111; CHECK-NEXT: br i1 [[AND_0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]112; CHECK: if.then:113; CHECK-NEXT: [[C_2:%.*]] = icmp sge i8 [[A]], 0114; CHECK-NEXT: [[C_3:%.*]] = icmp sge i8 [[B]], 0115; CHECK-NEXT: [[AND_1:%.*]] = and i1 [[C_2]], [[C_3]]116; CHECK-NEXT: br i1 [[AND_1]], label [[IF_THEN_2:%.*]], label [[IF_END]]117; CHECK: if.then.2:118; CHECK-NEXT: [[ADD_0:%.*]] = add nsw i8 [[A]], [[B]]119; CHECK-NEXT: call void @use(i1 true)120; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i8 [[A]], [[A]]121; CHECK-NEXT: call void @use(i1 true)122; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i8 [[A]], [[D:%.*]]123; CHECK-NEXT: [[C_4:%.*]] = icmp sge i8 [[ADD_2]], [[C]]124; CHECK-NEXT: call void @use(i1 [[C_4]])125; CHECK-NEXT: ret void126; CHECK: if.end:127; CHECK-NEXT: ret void128;129entry:130 %c.0 = icmp sge i8 %a, %c131 %c.1 = icmp sge i8 %b, %c132 %and.0 = and i1 %c.0, %c.1133 br i1 %and.0, label %if.then, label %if.end134 135if.then: ; preds = %entry136 %c.2 = icmp sge i8 %a, 0137 %c.3 = icmp sge i8 %b, 0138 %and.1 = and i1 %c.2, %c.3139 br i1 %and.1, label %if.then.2, label %if.end140 141if.then.2:142 %add.0 = add nsw i8 %a, %b143 %t.0 = icmp sge i8 %add.0, %c144 call void @use(i1 %t.0)145 %add.1 = add nsw i8 %a, %a146 %t.1 = icmp sge i8 %add.0, %c147 call void @use(i1 %t.1)148 %add.2 = add nsw i8 %a, %d149 %c.4 = icmp sge i8 %add.2, %c150 call void @use(i1 %c.4)151 ret void152 153if.end: ; preds = %entry154 ret void155}156 157define void @test.decompose.nonconst.no.null.check(i8 %a, i8 %b, i8 %c, i8 %d) {158; CHECK-LABEL: @test.decompose.nonconst.no.null.check(159; CHECK-NEXT: entry:160; CHECK-NEXT: [[C_0:%.*]] = icmp sge i8 [[A:%.*]], [[C:%.*]]161; CHECK-NEXT: [[C_1:%.*]] = icmp sge i8 [[B:%.*]], [[C]]162; CHECK-NEXT: [[AND_0:%.*]] = and i1 [[C_0]], [[C_1]]163; CHECK-NEXT: br i1 [[AND_0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]164; CHECK: if.then:165; CHECK-NEXT: [[ADD_0:%.*]] = add nsw i8 [[A]], [[B]]166; CHECK-NEXT: [[T_0:%.*]] = icmp sge i8 [[ADD_0]], [[C]]167; CHECK-NEXT: call void @use(i1 [[T_0]])168; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i8 [[A]], [[A]]169; CHECK-NEXT: [[T_1:%.*]] = icmp sge i8 [[ADD_0]], [[C]]170; CHECK-NEXT: call void @use(i1 [[T_1]])171; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i8 [[A]], [[D:%.*]]172; CHECK-NEXT: [[C_4:%.*]] = icmp sge i8 [[ADD_2]], [[C]]173; CHECK-NEXT: call void @use(i1 [[C_4]])174; CHECK-NEXT: ret void175; CHECK: if.end:176; CHECK-NEXT: ret void177;178entry:179 %c.0 = icmp sge i8 %a, %c180 %c.1 = icmp sge i8 %b, %c181 %and.0 = and i1 %c.0, %c.1182 br i1 %and.0, label %if.then, label %if.end183 184if.then: ; preds = %entry185 %add.0 = add nsw i8 %a, %b186 %t.0 = icmp sge i8 %add.0, %c187 call void @use(i1 %t.0)188 %add.1 = add nsw i8 %a, %a189 %t.1 = icmp sge i8 %add.0, %c190 call void @use(i1 %t.1)191 %add.2 = add nsw i8 %a, %d192 %c.4 = icmp sge i8 %add.2, %c193 call void @use(i1 %c.4)194 ret void195 196if.end: ; preds = %entry197 ret void198}199 200define void @test.sge.slt.add.neg(i8 %start, i8 %high) {201; CHECK-LABEL: @test.sge.slt.add.neg(202; CHECK-NEXT: entry:203; CHECK-NEXT: [[ADD_PTR_I:%.*]] = add nsw i8 [[START:%.*]], -3204; CHECK-NEXT: [[C_1:%.*]] = icmp slt i8 [[ADD_PTR_I]], [[HIGH:%.*]]205; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])206; CHECK-NEXT: [[C_2:%.*]] = icmp slt i8 [[START]], [[HIGH]]207; CHECK-NEXT: call void @use(i1 [[C_2]])208; CHECK-NEXT: [[START_1:%.*]] = add nsw i8 [[START]], 1209; CHECK-NEXT: [[C_3:%.*]] = icmp slt i8 [[START_1]], [[HIGH]]210; CHECK-NEXT: call void @use(i1 [[C_3]])211; CHECK-NEXT: [[START_2:%.*]] = add nsw i8 [[START]], -2212; CHECK-NEXT: [[C_4:%.*]] = icmp slt i8 [[START_2]], [[HIGH]]213; CHECK-NEXT: call void @use(i1 [[C_4]])214; CHECK-NEXT: [[START_3:%.*]] = add nsw i8 [[START]], -3215; CHECK-NEXT: call void @use(i1 true)216; CHECK-NEXT: [[START_4:%.*]] = add nsw i8 [[START]], -4217; CHECK-NEXT: call void @use(i1 true)218; CHECK-NEXT: ret void219;220entry:221 %add.ptr.i = add nsw i8 %start, -3222 %c.1 = icmp slt i8 %add.ptr.i, %high223 call void @llvm.assume(i1 %c.1)224 %c.2 = icmp slt i8 %start, %high225 call void @use(i1 %c.2)226 %start.1 = add nsw i8 %start, 1227 %c.3 = icmp slt i8 %start.1, %high228 call void @use(i1 %c.3)229 %start.2 = add nsw i8 %start, -2230 %c.4 = icmp slt i8 %start.2, %high231 call void @use(i1 %c.4)232 %start.3 = add nsw i8 %start, -3233 %t.1 = icmp slt i8 %start.3, %high234 call void @use(i1 %t.1)235 %start.4 = add nsw i8 %start, -4236 %t.2 = icmp slt i8 %start.4, %high237 call void @use(i1 %t.2)238 ret void239}240 241define i1 @test_ult_add_nsw_pos_1(i8 %start, i8 %high) {242; CHECK-LABEL: @test_ult_add_nsw_pos_1(243; CHECK-NEXT: entry:244; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16245; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16246; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3247; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]248; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])249; CHECK-NEXT: ret i1 true250;251entry:252 %high.ext = zext i8 %high to i16253 %start.ext = zext i8 %start to i16254 %add.ext = add nsw i16 %start.ext, 3255 %c.1 = icmp ult i16 %add.ext, %high.ext256 call void @llvm.assume(i1 %c.1)257 258 %t = icmp ult i16 %start.ext, %high.ext259 ret i1 %t260}261 262define i1 @test_ult_add_nsw_pos_1_assume_pos(i8 %start, i8 %high) {263; CHECK-LABEL: @test_ult_add_nsw_pos_1_assume_pos(264; CHECK-NEXT: entry:265; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0266; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])267; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], 3268; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]269; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])270; CHECK-NEXT: ret i1 true271;272entry:273 %start.pos = icmp sge i8 %start, 0274 call void @llvm.assume(i1 %start.pos)275 %add = add nsw i8 %start, 3276 %c.1 = icmp ult i8 %add, %high277 call void @llvm.assume(i1 %c.1)278 279 %t = icmp ult i8 %start, %high280 ret i1 %t281}282 283define i1 @test_ult_add_nsw_pos_1_no_assume_pos(i8 %start, i8 %high) {284; CHECK-LABEL: @test_ult_add_nsw_pos_1_no_assume_pos(285; CHECK-NEXT: entry:286; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START:%.*]], 3287; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]288; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])289; CHECK-NEXT: [[T:%.*]] = icmp ult i8 [[START]], [[HIGH]]290; CHECK-NEXT: ret i1 [[T]]291;292entry:293 %add = add nsw i8 %start, 3294 %c.1 = icmp ult i8 %add, %high295 call void @llvm.assume(i1 %c.1)296 297 %t = icmp ult i8 %start, %high298 ret i1 %t299}300 301define i1 @test_ult_add_nsw_pos_1_cmp_no_ext(i8 %start, i8 %high) {302; CHECK-LABEL: @test_ult_add_nsw_pos_1_cmp_no_ext(303; CHECK-NEXT: entry:304; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16305; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16306; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3307; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]308; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])309; CHECK-NEXT: ret i1 true310;311entry:312 %high.ext = zext i8 %high to i16313 %start.ext = zext i8 %start to i16314 %add.ext = add nsw i16 %start.ext, 3315 %c.1 = icmp ult i16 %add.ext, %high.ext316 call void @llvm.assume(i1 %c.1)317 318 %t = icmp ult i8 %start, %high319 ret i1 %t320}321 322define i1 @test_ult_add_nsw_pos_2(i8 %start, i8 %high) {323; CHECK-LABEL: @test_ult_add_nsw_pos_2(324; CHECK-NEXT: entry:325; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16326; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16327; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3328; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]329; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])330; CHECK-NEXT: ret i1 false331;332entry:333 %high.ext = zext i8 %high to i16334 %start.ext = zext i8 %start to i16335 %add.ext = add nsw i16 %start.ext, 3336 %c.1 = icmp ult i16 %add.ext, %high.ext337 call void @llvm.assume(i1 %c.1)338 339 %f = icmp uge i16 %start.ext, %high.ext340 ret i1 %f341}342 343define i1 @test_ult_add_nsw_pos_2_assume_pos(i8 %start, i8 %high) {344; CHECK-LABEL: @test_ult_add_nsw_pos_2_assume_pos(345; CHECK-NEXT: entry:346; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0347; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])348; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], 3349; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]350; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])351; CHECK-NEXT: ret i1 false352;353entry:354 %start.pos = icmp sge i8 %start, 0355 call void @llvm.assume(i1 %start.pos)356 %add = add nsw i8 %start, 3357 %c.1 = icmp ult i8 %add, %high358 call void @llvm.assume(i1 %c.1)359 360 %f = icmp uge i8 %start, %high361 ret i1 %f362}363 364define i1 @test_ult_add_nsw_pos_2_cmp_no_ext(i8 %start, i8 %high) {365; CHECK-LABEL: @test_ult_add_nsw_pos_2_cmp_no_ext(366; CHECK-NEXT: entry:367; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16368; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16369; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3370; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]371; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])372; CHECK-NEXT: ret i1 false373;374entry:375 %high.ext = zext i8 %high to i16376 %start.ext = zext i8 %start to i16377 %add.ext = add nsw i16 %start.ext, 3378 %c.1 = icmp ult i16 %add.ext, %high.ext379 call void @llvm.assume(i1 %c.1)380 381 %c = icmp uge i8 %start, %high382 ret i1 %c383}384 385define i1 @test_ult_add_nsw_pos_3(i8 %start, i8 %high) {386; CHECK-LABEL: @test_ult_add_nsw_pos_3(387; CHECK-NEXT: entry:388; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16389; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16390; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3391; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]392; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])393; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i16 [[START_EXT]], 4394; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[ADD_4]], [[HIGH_EXT]]395; CHECK-NEXT: ret i1 [[C]]396;397entry:398 %high.ext = zext i8 %high to i16399 %start.ext = zext i8 %start to i16400 %add.ext = add nsw i16 %start.ext, 3401 %c.1 = icmp ult i16 %add.ext, %high.ext402 call void @llvm.assume(i1 %c.1)403 404 %add.4 = add nsw i16 %start.ext, 4405 %c = icmp ult i16 %add.4, %high.ext406 ret i1 %c407}408 409define i1 @test_ult_add_nsw_pos_3_assume_pos(i8 %start, i8 %high) {410; CHECK-LABEL: @test_ult_add_nsw_pos_3_assume_pos(411; CHECK-NEXT: entry:412; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0413; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])414; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], 3415; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]416; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])417; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i8 [[START]], 4418; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[ADD_4]], [[HIGH]]419; CHECK-NEXT: ret i1 [[C]]420;421entry:422 %start.pos = icmp sge i8 %start, 0423 call void @llvm.assume(i1 %start.pos)424 %add = add nsw i8 %start, 3425 %c.1 = icmp ult i8 %add, %high426 call void @llvm.assume(i1 %c.1)427 428 %add.4 = add nsw i8 %start, 4429 %c = icmp ult i8 %add.4, %high430 ret i1 %c431}432 433define i1 @test_ult_add_nsw_pos_4(i8 %start, i8 %high) {434; CHECK-LABEL: @test_ult_add_nsw_pos_4(435; CHECK-NEXT: entry:436; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16437; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16438; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3439; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]440; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])441; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i16 [[START_EXT]], 2442; CHECK-NEXT: ret i1 true443;444entry:445 %high.ext = zext i8 %high to i16446 %start.ext = zext i8 %start to i16447 %add.ext = add nsw i16 %start.ext, 3448 %c.1 = icmp ult i16 %add.ext, %high.ext449 call void @llvm.assume(i1 %c.1)450 451 %add.2 = add nsw i16 %start.ext, 2452 %c = icmp ult i16 %add.2, %high.ext453 ret i1 %c454}455 456define i1 @test_ult_add_nsw_pos_4_assume_pos(i8 %start, i8 %high) {457; CHECK-LABEL: @test_ult_add_nsw_pos_4_assume_pos(458; CHECK-NEXT: entry:459; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0460; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])461; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], 3462; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]463; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])464; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i8 [[START]], 2465; CHECK-NEXT: ret i1 true466;467entry:468 %start.pos = icmp sge i8 %start, 0469 call void @llvm.assume(i1 %start.pos)470 %add = add nsw i8 %start, 3471 %c.1 = icmp ult i8 %add, %high472 call void @llvm.assume(i1 %c.1)473 474 %add.2 = add nsw i8 %start, 2475 %c = icmp ult i8 %add.2, %high476 ret i1 %c477}478 479define i1 @test_ult_add_nsw_neg_5(i8 %start, i8 %high) {480; CHECK-LABEL: @test_ult_add_nsw_neg_5(481; CHECK-NEXT: entry:482; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16483; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16484; CHECK-NEXT: [[ADD_EXT:%.*]] = add nsw i16 [[START_EXT]], 3485; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]486; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])487; CHECK-NEXT: [[SUB_2:%.*]] = add nsw i16 [[START_EXT]], -2488; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[SUB_2]], [[HIGH_EXT]]489; CHECK-NEXT: ret i1 [[C]]490;491entry:492 %high.ext = zext i8 %high to i16493 %start.ext = zext i8 %start to i16494 %add.ext = add nsw i16 %start.ext, 3495 %c.1 = icmp ult i16 %add.ext, %high.ext496 call void @llvm.assume(i1 %c.1)497 498 %sub.2 = add nsw i16 %start.ext, -2499 %c = icmp ult i16 %sub.2, %high.ext500 ret i1 %c501}502 503define i1 @test_ult_add_nsw_neg_5_assume_pos(i8 %start, i8 %high) {504; CHECK-LABEL: @test_ult_add_nsw_neg_5_assume_pos(505; CHECK-NEXT: entry:506; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0507; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])508; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], 3509; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]510; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])511; CHECK-NEXT: [[SUB_2:%.*]] = add nsw i8 [[START]], -2512; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[SUB_2]], [[HIGH]]513; CHECK-NEXT: ret i1 [[C]]514;515entry:516 %start.pos = icmp sge i8 %start, 0517 call void @llvm.assume(i1 %start.pos)518 %add = add nsw i8 %start, 3519 %c.1 = icmp ult i8 %add, %high520 call void @llvm.assume(i1 %c.1)521 522 %sub.2 = add nsw i8 %start, -2523 %c = icmp ult i8 %sub.2, %high524 ret i1 %c525}526 527define i1 @test_ult_add_no_nsw_pos_6(i8 %start, i8 %high) {528; CHECK-LABEL: @test_ult_add_no_nsw_pos_6(529; CHECK-NEXT: entry:530; CHECK-NEXT: [[HIGH_EXT:%.*]] = zext i8 [[HIGH:%.*]] to i16531; CHECK-NEXT: [[START_EXT:%.*]] = zext i8 [[START:%.*]] to i16532; CHECK-NEXT: [[ADD_EXT:%.*]] = add i16 [[START_EXT]], 3533; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[ADD_EXT]], [[HIGH_EXT]]534; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])535; CHECK-NEXT: [[ADD_2:%.*]] = add i16 [[START_EXT]], 2536; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[ADD_2]], [[HIGH_EXT]]537; CHECK-NEXT: ret i1 [[C]]538;539entry:540 %high.ext = zext i8 %high to i16541 %start.ext = zext i8 %start to i16542 %add.ext = add i16 %start.ext, 3543 %c.1 = icmp ult i16 %add.ext, %high.ext544 call void @llvm.assume(i1 %c.1)545 546 %add.2 = add i16 %start.ext, 2547 %c = icmp ult i16 %add.2, %high.ext548 ret i1 %c549}550 551define i1 @test_ult_add_no_nsw_pos_6_assume_pos(i8 %start, i8 %high) {552; CHECK-LABEL: @test_ult_add_no_nsw_pos_6_assume_pos(553; CHECK-NEXT: entry:554; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0555; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])556; CHECK-NEXT: [[ADD:%.*]] = add i8 [[START]], 3557; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]558; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])559; CHECK-NEXT: [[ADD_2:%.*]] = add i8 [[START]], 2560; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[ADD_2]], [[HIGH]]561; CHECK-NEXT: ret i1 [[C]]562;563entry:564 %start.pos = icmp sge i8 %start, 0565 call void @llvm.assume(i1 %start.pos)566 %add = add i8 %start, 3567 %c.1 = icmp ult i8 %add, %high568 call void @llvm.assume(i1 %c.1)569 570 %add.2 = add i8 %start, 2571 %c = icmp ult i8 %add.2, %high572 ret i1 %c573}574 575define i1 @test_ult_add_nsw_var_7(i8 %start, i8 %off, i8 %high) {576; CHECK-LABEL: @test_ult_add_nsw_var_7(577; CHECK-NEXT: entry:578; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START:%.*]], [[OFF:%.*]]579; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]580; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])581; CHECK-NEXT: [[OFF_POS:%.*]] = icmp sge i8 [[OFF]], 0582; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_POS]])583; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[START]], [[HIGH]]584; CHECK-NEXT: ret i1 [[C]]585;586entry:587 %add = add nsw i8 %start, %off588 %c.1 = icmp ult i8 %add, %high589 call void @llvm.assume(i1 %c.1)590 %off.pos = icmp sge i8 %off, 0591 call void @llvm.assume(i1 %off.pos)592 593 %c = icmp ult i8 %start, %high594 ret i1 %c595}596 597define i1 @test_ult_add_no_nsw_var_7(i8 %start, i8 %off, i8 %high) {598; CHECK-LABEL: @test_ult_add_no_nsw_var_7(599; CHECK-NEXT: entry:600; CHECK-NEXT: [[ADD:%.*]] = add i8 [[START:%.*]], [[OFF:%.*]]601; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]602; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])603; CHECK-NEXT: [[OFF_POS:%.*]] = icmp sge i8 [[OFF]], 0604; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_POS]])605; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[START]], [[HIGH]]606; CHECK-NEXT: ret i1 [[C]]607;608entry:609 %add = add i8 %start, %off610 %c.1 = icmp ult i8 %add, %high611 call void @llvm.assume(i1 %c.1)612 %off.pos = icmp sge i8 %off, 0613 call void @llvm.assume(i1 %off.pos)614 615 %c = icmp ult i8 %start, %high616 ret i1 %c617}618 619define i1 @test_ult_add_nsw_var_8(i8 %start, i8 %off.1, i8 %off.2, i8 %high) {620; CHECK-LABEL: @test_ult_add_nsw_var_8(621; CHECK-NEXT: entry:622; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START:%.*]], [[OFF_2:%.*]]623; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]624; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])625; CHECK-NEXT: [[OFF_1_POS:%.*]] = icmp sge i8 [[OFF_1:%.*]], 0626; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_POS]])627; CHECK-NEXT: [[OFF_2_POS:%.*]] = icmp sge i8 [[OFF_2]], 0628; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_2_POS]])629; CHECK-NEXT: [[OFF_1_ULT:%.*]] = icmp ult i8 [[OFF_1]], [[OFF_2]]630; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_ULT]])631; CHECK-NEXT: [[ADD_OFF_2:%.*]] = add nsw i8 [[START]], [[OFF_1]]632; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[ADD_OFF_2]], [[HIGH]]633; CHECK-NEXT: ret i1 [[C]]634;635entry:636 %add = add nsw i8 %start, %off.2637 %c.1 = icmp ult i8 %add, %high638 call void @llvm.assume(i1 %c.1)639 %off.1.pos = icmp sge i8 %off.1, 0640 call void @llvm.assume(i1 %off.1.pos)641 %off.2.pos = icmp sge i8 %off.2, 0642 call void @llvm.assume(i1 %off.2.pos)643 %off.1.ult = icmp ult i8 %off.1, %off.2644 call void @llvm.assume(i1 %off.1.ult)645 646 %add.off.2 = add nsw i8 %start, %off.1647 %c = icmp ult i8 %add.off.2, %high648 ret i1 %c649}650 651define i1 @test_ult_add_nsw_var_8_all_pos(i8 %start, i8 %off.1, i8 %off.2, i8 %high) {652; CHECK-LABEL: @test_ult_add_nsw_var_8_all_pos(653; CHECK-NEXT: entry:654; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0655; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])656; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], [[OFF_2:%.*]]657; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]658; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])659; CHECK-NEXT: [[OFF_1_POS:%.*]] = icmp sge i8 [[OFF_1:%.*]], 0660; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_POS]])661; CHECK-NEXT: [[OFF_2_POS:%.*]] = icmp sge i8 [[OFF_2]], 0662; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_2_POS]])663; CHECK-NEXT: [[OFF_1_ULT:%.*]] = icmp ult i8 [[OFF_1]], [[OFF_2]]664; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_ULT]])665; CHECK-NEXT: [[ADD_OFF_2:%.*]] = add nsw i8 [[START]], [[OFF_1]]666; CHECK-NEXT: ret i1 true667;668entry:669 %start.pos = icmp sge i8 %start, 0670 call void @llvm.assume(i1 %start.pos)671 %add = add nsw i8 %start, %off.2672 %c.1 = icmp ult i8 %add, %high673 call void @llvm.assume(i1 %c.1)674 %off.1.pos = icmp sge i8 %off.1, 0675 call void @llvm.assume(i1 %off.1.pos)676 %off.2.pos = icmp sge i8 %off.2, 0677 call void @llvm.assume(i1 %off.2.pos)678 %off.1.ult = icmp ult i8 %off.1, %off.2679 call void @llvm.assume(i1 %off.1.ult)680 681 %add.off.2 = add nsw i8 %start, %off.1682 %c = icmp ult i8 %add.off.2, %high683 ret i1 %c684}685 686define i1 @test_ult_add_no_nsw_var_8_all_pos(i8 %start, i8 %off.1, i8 %off.2, i8 %high) {687; CHECK-LABEL: @test_ult_add_no_nsw_var_8_all_pos(688; CHECK-NEXT: entry:689; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0690; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])691; CHECK-NEXT: [[ADD:%.*]] = add i8 [[START]], [[OFF_2:%.*]]692; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]693; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])694; CHECK-NEXT: [[OFF_1_POS:%.*]] = icmp sge i8 [[OFF_1:%.*]], 0695; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_POS]])696; CHECK-NEXT: [[OFF_2_POS:%.*]] = icmp sge i8 [[OFF_2]], 0697; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_2_POS]])698; CHECK-NEXT: [[OFF_1_ULT:%.*]] = icmp ult i8 [[OFF_1]], [[OFF_2]]699; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_ULT]])700; CHECK-NEXT: [[ADD_OFF_2:%.*]] = add nsw i8 [[START]], [[OFF_1]]701; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[ADD_OFF_2]], [[HIGH]]702; CHECK-NEXT: ret i1 [[C]]703;704entry:705 %start.pos = icmp sge i8 %start, 0706 call void @llvm.assume(i1 %start.pos)707 %add = add i8 %start, %off.2708 %c.1 = icmp ult i8 %add, %high709 call void @llvm.assume(i1 %c.1)710 %off.1.pos = icmp sge i8 %off.1, 0711 call void @llvm.assume(i1 %off.1.pos)712 %off.2.pos = icmp sge i8 %off.2, 0713 call void @llvm.assume(i1 %off.2.pos)714 %off.1.ult = icmp ult i8 %off.1, %off.2715 call void @llvm.assume(i1 %off.1.ult)716 717 %add.off.2 = add nsw i8 %start, %off.1718 %c = icmp ult i8 %add.off.2, %high719 ret i1 %c720}721 722define i1 @test_ult_add_nsw_var_9_all_pos(i8 %start, i8 %off.1, i8 %off.2, i8 %high) {723; CHECK-LABEL: @test_ult_add_nsw_var_9_all_pos(724; CHECK-NEXT: entry:725; CHECK-NEXT: [[START_POS:%.*]] = icmp sge i8 [[START:%.*]], 0726; CHECK-NEXT: call void @llvm.assume(i1 [[START_POS]])727; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[START]], [[OFF_2:%.*]]728; CHECK-NEXT: [[C_1:%.*]] = icmp ult i8 [[ADD]], [[HIGH:%.*]]729; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])730; CHECK-NEXT: [[OFF_1_POS:%.*]] = icmp sge i8 [[OFF_1:%.*]], 0731; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_1_POS]])732; CHECK-NEXT: [[OFF_2_POS:%.*]] = icmp sge i8 [[OFF_2]], 0733; CHECK-NEXT: call void @llvm.assume(i1 [[OFF_2_POS]])734; CHECK-NEXT: [[ADD_OFF_2:%.*]] = add nsw i8 [[START]], [[OFF_1]]735; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[ADD_OFF_2]], [[HIGH]]736; CHECK-NEXT: ret i1 [[C]]737;738entry:739 %start.pos = icmp sge i8 %start, 0740 call void @llvm.assume(i1 %start.pos)741 %add = add nsw i8 %start, %off.2742 %c.1 = icmp ult i8 %add, %high743 call void @llvm.assume(i1 %c.1)744 %off.1.pos = icmp sge i8 %off.1, 0745 call void @llvm.assume(i1 %off.1.pos)746 %off.2.pos = icmp sge i8 %off.2, 0747 call void @llvm.assume(i1 %off.2.pos)748 749 %add.off.2 = add nsw i8 %start, %off.1750 %c = icmp ult i8 %add.off.2, %high751 ret i1 %c752}753 754define i1 @add_neg_1_known_sge_ult_1(i32 %a) {755; CHECK-LABEL: @add_neg_1_known_sge_ult_1(756; CHECK-NEXT: entry:757; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 1758; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])759; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -1760; CHECK-NEXT: ret i1 true761;762entry:763 %a.sge = icmp sge i32 %a, 1764 call void @llvm.assume(i1 %a.sge)765 %sub = add nsw i32 %a, -1766 %c = icmp ult i32 %sub, %a767 ret i1 %c768}769 770define i1 @add_neg_1_known_sge_uge_1(i32 %a) {771; CHECK-LABEL: @add_neg_1_known_sge_uge_1(772; CHECK-NEXT: entry:773; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 1774; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])775; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -1776; CHECK-NEXT: ret i1 true777;778entry:779 %a.sge = icmp sge i32 %a, 1780 call void @llvm.assume(i1 %a.sge)781 %sub = add nsw i32 %a, -1782 %c = icmp uge i32 %sub, 0783 ret i1 %c784}785 786define i1 @add_neg_1_not_known_sge_ult_1(i32 %a) {787; CHECK-LABEL: @add_neg_1_not_known_sge_ult_1(788; CHECK-NEXT: entry:789; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 0790; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])791; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -1792; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[SUB]], [[A]]793; CHECK-NEXT: ret i1 [[C]]794;795entry:796 %a.sge = icmp sge i32 %a, 0797 call void @llvm.assume(i1 %a.sge)798 %sub = add nsw i32 %a, -1799 %c = icmp ult i32 %sub, %a800 ret i1 %c801}802 803define i1 @add_neg_1_not_known_sge_uge_1(i32 %a) {804; CHECK-LABEL: @add_neg_1_not_known_sge_uge_1(805; CHECK-NEXT: entry:806; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 0807; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])808; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -1809; CHECK-NEXT: ret i1 true810;811entry:812 %a.sge = icmp sge i32 %a, 0813 call void @llvm.assume(i1 %a.sge)814 %sub = add nsw i32 %a, -1815 %c = icmp uge i32 %sub, 0816 ret i1 %c817}818 819define i1 @add_neg_3_known_sge_ult_1(i32 %a) {820; CHECK-LABEL: @add_neg_3_known_sge_ult_1(821; CHECK-NEXT: entry:822; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 3823; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])824; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -3825; CHECK-NEXT: ret i1 true826;827entry:828 %a.sge = icmp sge i32 %a, 3829 call void @llvm.assume(i1 %a.sge)830 %sub = add nsw i32 %a, -3831 %c = icmp ult i32 %sub, %a832 ret i1 %c833}834 835define i1 @add_neg_3_known_sge_uge_1(i32 %a) {836; CHECK-LABEL: @add_neg_3_known_sge_uge_1(837; CHECK-NEXT: entry:838; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 4839; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])840; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -3841; CHECK-NEXT: ret i1 true842;843entry:844 %a.sge = icmp sge i32 %a, 4845 call void @llvm.assume(i1 %a.sge)846 %sub = add nsw i32 %a, -3847 %c = icmp uge i32 %sub, 0848 ret i1 %c849}850 851define i1 @add_neg_3_not_known_sge_ult_1(i32 %a) {852; CHECK-LABEL: @add_neg_3_not_known_sge_ult_1(853; CHECK-NEXT: entry:854; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 2855; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])856; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -3857; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[SUB]], [[A]]858; CHECK-NEXT: ret i1 [[C]]859;860entry:861 %a.sge = icmp sge i32 %a, 2862 call void @llvm.assume(i1 %a.sge)863 %sub = add nsw i32 %a, -3864 %c = icmp ult i32 %sub, %a865 ret i1 %c866}867 868define i1 @add_neg_3_not_known_sge_uge_1(i32 %a) {869; CHECK-LABEL: @add_neg_3_not_known_sge_uge_1(870; CHECK-NEXT: entry:871; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], 2872; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])873; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -3874; CHECK-NEXT: ret i1 true875;876entry:877 %a.sge = icmp sge i32 %a, 2878 call void @llvm.assume(i1 %a.sge)879 %sub = add nsw i32 %a, -3880 %c = icmp uge i32 %sub, 0881 ret i1 %c882}883 884define i1 @add_neg_3_not_known_sge_ult_2(i32 %a, i32 %b) {885; CHECK-LABEL: @add_neg_3_not_known_sge_ult_2(886; CHECK-NEXT: entry:887; CHECK-NEXT: [[A_SGE:%.*]] = icmp sge i32 [[A:%.*]], [[B:%.*]]888; CHECK-NEXT: call void @llvm.assume(i1 [[A_SGE]])889; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[A]], -3890; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[SUB]], [[A]]891; CHECK-NEXT: ret i1 [[C]]892;893entry:894 %a.sge = icmp sge i32 %a, %b895 call void @llvm.assume(i1 %a.sge)896 %sub = add nsw i32 %a, -3897 %c = icmp ult i32 %sub, %a898 ret i1 %c899}900