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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s3 4declare void @llvm.assume(i1 noundef) #05 6define i1 @n_unknown(ptr %dst, i32 %n, i32 %i) {7; CHECK-LABEL: @n_unknown(8; CHECK-NEXT: entry:9; CHECK-NEXT: [[SUB:%.*]] = add i32 [[N:%.*]], -110; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[SUB]] to i6411; CHECK-NEXT: [[PTR_N_SUB_1:%.*]] = getelementptr i32, ptr [[DST:%.*]], i64 [[IDXPROM]]12; CHECK-NEXT: [[CMP_PTR_DST:%.*]] = icmp sge ptr [[PTR_N_SUB_1]], [[DST]]13; CHECK-NEXT: br i1 [[CMP_PTR_DST]], label [[PRE_BB_2:%.*]], label [[EXIT:%.*]]14; CHECK: exit:15; CHECK-NEXT: ret i1 false16; CHECK: pre.bb.2:17; CHECK-NEXT: [[PRE_2:%.*]] = icmp sge i32 [[I:%.*]], 018; CHECK-NEXT: br i1 [[PRE_2]], label [[TGT_BB:%.*]], label [[EXIT]]19; CHECK: tgt.bb:20; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[I]], [[N]]21; CHECK-NEXT: ret i1 [[CMP1]]22;23entry:24 %sub = add i32 %n, -125 %idxprom = zext i32 %sub to i6426 %ptr.n.sub.1 = getelementptr i32, ptr %dst, i64 %idxprom27 %cmp.ptr.dst = icmp sge ptr %ptr.n.sub.1, %dst28 br i1 %cmp.ptr.dst, label %pre.bb.2, label %exit29 30exit:31 ret i1 false32 33pre.bb.2:34 %pre.2 = icmp sge i32 %i, 035 br i1 %pre.2, label %tgt.bb, label %exit36 37tgt.bb:38 %cmp1 = icmp slt i32 %i, %n39 ret i1 %cmp140}41 42define i1 @n_known_zero_due_to_nuw(ptr %dst, i32 %n, i32 %i) {43; CHECK-LABEL: @n_known_zero_due_to_nuw(44; CHECK-NEXT: entry:45; CHECK-NEXT: [[SUB:%.*]] = add i32 [[N:%.*]], -146; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[SUB]] to i6447; CHECK-NEXT: [[PTR_N_SUB_1:%.*]] = getelementptr i32, ptr [[DST:%.*]], i64 [[IDXPROM]]48; CHECK-NEXT: [[CMP_PTR_DST:%.*]] = icmp sge ptr [[PTR_N_SUB_1]], [[DST]]49; CHECK-NEXT: br i1 [[CMP_PTR_DST]], label [[PRE_BB_2:%.*]], label [[EXIT:%.*]]50; CHECK: exit:51; CHECK-NEXT: ret i1 false52; CHECK: pre.bb.2:53; CHECK-NEXT: [[PRE_2:%.*]] = icmp sge i32 [[I:%.*]], 054; CHECK-NEXT: br i1 [[PRE_2]], label [[TGT_BB:%.*]], label [[EXIT]]55; CHECK: tgt.bb:56; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[I]], [[N]]57; CHECK-NEXT: ret i1 [[CMP1]]58;59entry:60 %sub = add i32 %n, -161 %idxprom = zext i32 %sub to i6462 %ptr.n.sub.1 = getelementptr i32, ptr %dst, i64 %idxprom63 %cmp.ptr.dst = icmp sge ptr %ptr.n.sub.1, %dst64 br i1 %cmp.ptr.dst, label %pre.bb.2, label %exit65 66exit:67 ret i1 false68 69pre.bb.2:70 %pre.2 = icmp sge i32 %i, 071 br i1 %pre.2, label %tgt.bb, label %exit72 73tgt.bb:74 %cmp1 = icmp slt i32 %i, %n75 ret i1 %cmp176}77 78define i4 @inc_ptr_N_could_be_negative(ptr %src, ptr %lower, ptr %upper, i8 %N, i8 %step) {79; CHECK-LABEL: @inc_ptr_N_could_be_negative(80; CHECK-NEXT: entry:81; CHECK-NEXT: [[SRC_END:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i8 [[N:%.*]]82; CHECK-NEXT: [[CMP_SRC_START:%.*]] = icmp slt ptr [[SRC]], [[LOWER:%.*]]83; CHECK-NEXT: [[CMP_SRC_END:%.*]] = icmp sge ptr [[SRC_END]], [[UPPER:%.*]]84; CHECK-NEXT: [[OR_PRECOND_0:%.*]] = or i1 [[CMP_SRC_START]], [[CMP_SRC_END]]85; CHECK-NEXT: br i1 [[OR_PRECOND_0]], label [[TRAP_BB:%.*]], label [[STEP_CHECK:%.*]]86; CHECK: trap.bb:87; CHECK-NEXT: ret i4 288; CHECK: step.check:89; CHECK-NEXT: [[STEP_POS:%.*]] = icmp sge i8 [[STEP:%.*]], 090; CHECK-NEXT: [[NEXT:%.*]] = add nuw nsw i8 [[STEP]], 291; CHECK-NEXT: [[STEP_SLT_N:%.*]] = icmp slt i8 [[NEXT]], [[N]]92; CHECK-NEXT: [[AND_STEP:%.*]] = and i1 [[STEP_POS]], [[STEP_SLT_N]]93; CHECK-NEXT: br i1 [[AND_STEP]], label [[PTR_CHECK:%.*]], label [[EXIT:%.*]]94; CHECK: ptr.check:95; CHECK-NEXT: [[SRC_STEP:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i8 [[STEP]]96; CHECK-NEXT: [[CMP_STEP_START:%.*]] = icmp slt ptr [[SRC_STEP]], [[LOWER]]97; CHECK-NEXT: [[CMP_STEP_END:%.*]] = icmp sge ptr [[SRC_STEP]], [[UPPER]]98; CHECK-NEXT: [[OR_CHECK:%.*]] = or i1 [[CMP_STEP_START]], [[CMP_STEP_END]]99; CHECK-NEXT: br i1 [[OR_CHECK]], label [[TRAP_BB]], label [[EXIT]]100; CHECK: exit:101; CHECK-NEXT: ret i4 3102;103entry:104 %src.end = getelementptr inbounds i8, ptr %src, i8 %N105 %cmp.src.start = icmp slt ptr %src, %lower106 %cmp.src.end = icmp sge ptr %src.end, %upper107 %or.precond.0 = or i1 %cmp.src.start, %cmp.src.end108 br i1 %or.precond.0, label %trap.bb, label %step.check109 110trap.bb:111 ret i4 2112 113step.check:114 %step.pos = icmp sge i8 %step, 0115 %next = add nuw nsw i8 %step, 2116 %step.slt.N = icmp slt i8 %next, %N117 %and.step = and i1 %step.pos, %step.slt.N118 br i1 %and.step, label %ptr.check, label %exit119 120ptr.check:121 %src.step = getelementptr inbounds i8, ptr %src, i8 %step122 %cmp.step.start = icmp slt ptr %src.step, %lower123 %cmp.step.end = icmp sge ptr %src.step, %upper124 %or.check = or i1 %cmp.step.start, %cmp.step.end125 br i1 %or.check, label %trap.bb, label %exit126 127exit:128 ret i4 3129}130 131define i4 @inc_ptr_src_sge_end(ptr %src, ptr %lower, ptr %upper, i16 %N, i16 %step) {132; CHECK-LABEL: @inc_ptr_src_sge_end(133; CHECK-NEXT: entry:134; CHECK-NEXT: [[SRC_END:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i16 [[N:%.*]]135; CHECK-NEXT: [[CMP_SRC_START:%.*]] = icmp slt ptr [[SRC]], [[LOWER:%.*]]136; CHECK-NEXT: [[CMP_SRC_END:%.*]] = icmp sge ptr [[SRC_END]], [[UPPER:%.*]]137; CHECK-NEXT: [[CMP_OVERFLOW:%.*]] = icmp sgt ptr [[SRC]], [[SRC_END]]138; CHECK-NEXT: [[OR_PRECOND_0:%.*]] = or i1 [[CMP_SRC_START]], [[CMP_SRC_END]]139; CHECK-NEXT: [[OR_PRECOND_1:%.*]] = or i1 [[OR_PRECOND_0]], [[CMP_OVERFLOW]]140; CHECK-NEXT: br i1 [[OR_PRECOND_1]], label [[TRAP_BB:%.*]], label [[STEP_CHECK:%.*]]141; CHECK: trap.bb:142; CHECK-NEXT: ret i4 2143; CHECK: step.check:144; CHECK-NEXT: [[STEP_POS:%.*]] = icmp sge i16 [[STEP:%.*]], 0145; CHECK-NEXT: [[NEXT:%.*]] = add nuw nsw i16 [[STEP]], 2146; CHECK-NEXT: [[STEP_SLT_N:%.*]] = icmp slt i16 [[NEXT]], [[N]]147; CHECK-NEXT: [[AND_STEP:%.*]] = and i1 [[STEP_POS]], [[STEP_SLT_N]]148; CHECK-NEXT: br i1 [[AND_STEP]], label [[PTR_CHECK:%.*]], label [[EXIT:%.*]]149; CHECK: ptr.check:150; CHECK-NEXT: [[SRC_STEP:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i16 [[STEP]]151; CHECK-NEXT: [[CMP_STEP_START:%.*]] = icmp slt ptr [[SRC_STEP]], [[LOWER]]152; CHECK-NEXT: [[CMP_STEP_END:%.*]] = icmp sge ptr [[SRC_STEP]], [[UPPER]]153; CHECK-NEXT: [[OR_CHECK:%.*]] = or i1 [[CMP_STEP_START]], [[CMP_STEP_END]]154; CHECK-NEXT: br i1 [[OR_CHECK]], label [[TRAP_BB]], label [[EXIT]]155; CHECK: exit:156; CHECK-NEXT: ret i4 3157;158entry:159 %src.end = getelementptr inbounds i8, ptr %src, i16 %N160 %cmp.src.start = icmp slt ptr %src, %lower161 %cmp.src.end = icmp sge ptr %src.end, %upper162 %cmp.overflow = icmp sgt ptr %src, %src.end163 %or.precond.0 = or i1 %cmp.src.start, %cmp.src.end164 %or.precond.1 = or i1 %or.precond.0, %cmp.overflow165 br i1 %or.precond.1, label %trap.bb, label %step.check166 167trap.bb:168 ret i4 2169 170step.check:171 %step.pos = icmp sge i16 %step, 0172 %next = add nuw nsw i16 %step, 2173 %step.slt.N = icmp slt i16 %next, %N174 %and.step = and i1 %step.pos, %step.slt.N175 br i1 %and.step, label %ptr.check, label %exit176 177ptr.check:178 %src.step = getelementptr inbounds i8, ptr %src, i16 %step179 %cmp.step.start = icmp slt ptr %src.step, %lower180 %cmp.step.end = icmp sge ptr %src.step, %upper181 %or.check = or i1 %cmp.step.start, %cmp.step.end182 br i1 %or.check, label %trap.bb, label %exit183 184exit:185 ret i4 3186}187 188define i4 @inc_ptr_src_sge_end_no_nsw_add(ptr %src, ptr %lower, ptr %upper, i16 %idx, i16 %N, i16 %step) {189; CHECK-LABEL: @inc_ptr_src_sge_end_no_nsw_add(190; CHECK-NEXT: entry.1:191; CHECK-NEXT: [[IDX_POS:%.*]] = icmp sge i16 [[IDX:%.*]], 0192; CHECK-NEXT: br i1 [[IDX_POS]], label [[ENTRY:%.*]], label [[TRAP_BB:%.*]]193; CHECK: entry:194; CHECK-NEXT: [[SRC_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i16 [[IDX]]195; CHECK-NEXT: [[CMP_SRC_START:%.*]] = icmp slt ptr [[SRC_IDX]], [[LOWER:%.*]]196; CHECK-NEXT: br i1 [[CMP_SRC_START]], label [[TRAP_BB]], label [[STEP_CHECK:%.*]]197; CHECK: trap.bb:198; CHECK-NEXT: ret i4 2199; CHECK: step.check:200; CHECK-NEXT: [[NEXT:%.*]] = add i16 [[IDX]], 2201; CHECK-NEXT: [[SRC_STEP:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i16 [[NEXT]]202; CHECK-NEXT: [[CMP_STEP_START:%.*]] = icmp slt ptr [[SRC_STEP]], [[LOWER]]203; CHECK-NEXT: [[CMP_STEP_END:%.*]] = icmp sge ptr [[SRC_STEP]], [[UPPER:%.*]]204; CHECK-NEXT: [[OR_CHECK:%.*]] = or i1 [[CMP_STEP_START]], [[CMP_STEP_END]]205; CHECK-NEXT: br i1 [[OR_CHECK]], label [[TRAP_BB]], label [[EXIT:%.*]]206; CHECK: exit:207; CHECK-NEXT: ret i4 3208;209entry.1:210 %idx.pos = icmp sge i16 %idx, 0211 br i1 %idx.pos, label %entry, label %trap.bb212 213entry:214 %src.idx = getelementptr inbounds i8, ptr %src, i16 %idx215 %cmp.src.start = icmp slt ptr %src.idx, %lower216 br i1 %cmp.src.start, label %trap.bb, label %step.check217 218trap.bb:219 ret i4 2220 221step.check:222 %next = add i16 %idx, 2223 %src.step = getelementptr inbounds i8, ptr %src, i16 %next224 %cmp.step.start = icmp slt ptr %src.step, %lower225 %cmp.step.end = icmp sge ptr %src.step, %upper226 %or.check = or i1 %cmp.step.start, %cmp.step.end227 br i1 %or.check, label %trap.bb, label %exit228 229exit:230 ret i4 3231}232 233define i4 @inc_ptr_src_sge_end_no_nsw_add_sge_0(ptr %src, ptr %lower, ptr %upper, i16 %idx, i16 %N, i16 %step) {234; CHECK-LABEL: @inc_ptr_src_sge_end_no_nsw_add_sge_0(235; CHECK-NEXT: entry.1:236; CHECK-NEXT: [[IDX_POS:%.*]] = icmp sge i16 [[IDX:%.*]], 0237; CHECK-NEXT: br i1 [[IDX_POS]], label [[ENTRY:%.*]], label [[TRAP_BB:%.*]]238; CHECK: entry:239; CHECK-NEXT: [[SRC_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i16 [[IDX]]240; CHECK-NEXT: [[CMP_SRC_START:%.*]] = icmp slt ptr [[SRC_IDX]], [[LOWER:%.*]]241; CHECK-NEXT: br i1 [[CMP_SRC_START]], label [[TRAP_BB]], label [[STEP_CHECK:%.*]]242; CHECK: trap.bb:243; CHECK-NEXT: ret i4 2244; CHECK: step.check:245; CHECK-NEXT: [[NEXT:%.*]] = add i16 [[IDX]], 2246; CHECK-NEXT: [[SRC_STEP:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i16 [[NEXT]]247; CHECK-NEXT: [[CMP_STEP_START:%.*]] = icmp slt ptr [[SRC_STEP]], [[LOWER]]248; CHECK-NEXT: [[CMP_STEP_END:%.*]] = icmp sge ptr [[SRC_STEP]], [[UPPER:%.*]]249; CHECK-NEXT: [[OR_CHECK:%.*]] = or i1 [[CMP_STEP_START]], [[CMP_STEP_END]]250; CHECK-NEXT: br i1 [[OR_CHECK]], label [[TRAP_BB]], label [[EXIT:%.*]]251; CHECK: exit:252; CHECK-NEXT: ret i4 3253;254entry.1:255 %idx.pos = icmp sge i16 %idx, 0256 br i1 %idx.pos, label %entry, label %trap.bb257 258entry:259 %src.idx = getelementptr inbounds i8, ptr %src, i16 %idx260 %cmp.src.start = icmp slt ptr %src.idx, %lower261 br i1 %cmp.src.start, label %trap.bb, label %step.check262 263trap.bb:264 ret i4 2265 266step.check:267 %next = add i16 %idx, 2268 %src.step = getelementptr inbounds i8, ptr %src, i16 %next269 %cmp.step.start = icmp slt ptr %src.step, %lower270 %cmp.step.end = icmp sge ptr %src.step, %upper271 %or.check = or i1 %cmp.step.start, %cmp.step.end272 br i1 %or.check, label %trap.bb, label %exit273 274exit:275 ret i4 3276}277define i4 @ptr_N_step_zext_n_zext(ptr %src, ptr %lower, ptr %upper, i16 %N, i16 %step) {278; CHECK-LABEL: @ptr_N_step_zext_n_zext(279; CHECK-NEXT: entry:280; CHECK-NEXT: [[N_ADD_1:%.*]] = add nuw nsw i16 [[N:%.*]], 1281; CHECK-NEXT: [[N_ADD_1_EXT:%.*]] = zext i16 [[N_ADD_1]] to i32282; CHECK-NEXT: [[SRC_END:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i32 [[N_ADD_1_EXT]]283; CHECK-NEXT: [[CMP_SRC_START:%.*]] = icmp slt ptr [[SRC]], [[LOWER:%.*]]284; CHECK-NEXT: [[CMP_SRC_END:%.*]] = icmp sge ptr [[SRC_END]], [[UPPER:%.*]]285; CHECK-NEXT: [[OR_PRECOND_0:%.*]] = or i1 [[CMP_SRC_START]], [[CMP_SRC_END]]286; CHECK-NEXT: br i1 [[OR_PRECOND_0]], label [[TRAP_BB:%.*]], label [[STEP_CHECK:%.*]]287; CHECK: trap.bb:288; CHECK-NEXT: ret i4 2289; CHECK: step.check:290; CHECK-NEXT: [[STEP_ADD_1:%.*]] = add nuw nsw i16 [[STEP:%.*]], 1291; CHECK-NEXT: [[STEP_ADD_1_EXT:%.*]] = zext i16 [[STEP_ADD_1]] to i32292; CHECK-NEXT: [[STEP_SLT_N:%.*]] = icmp slt i32 [[STEP_ADD_1_EXT]], [[N_ADD_1_EXT]]293; CHECK-NEXT: br i1 [[STEP_SLT_N]], label [[PTR_CHECK:%.*]], label [[EXIT:%.*]]294; CHECK: ptr.check:295; CHECK-NEXT: [[SRC_STEP:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i32 [[STEP_ADD_1_EXT]]296; CHECK-NEXT: [[CMP_STEP_START:%.*]] = icmp slt ptr [[SRC_STEP]], [[LOWER]]297; CHECK-NEXT: [[CMP_STEP_END:%.*]] = icmp sge ptr [[SRC_STEP]], [[UPPER]]298; CHECK-NEXT: [[OR_CHECK:%.*]] = or i1 [[CMP_STEP_START]], [[CMP_STEP_END]]299; CHECK-NEXT: br i1 [[OR_CHECK]], label [[TRAP_BB]], label [[EXIT]]300; CHECK: exit:301; CHECK-NEXT: ret i4 3302;303entry:304 %N.add.1 = add nuw nsw i16 %N, 1305 %N.add.1.ext = zext i16 %N.add.1 to i32306 %src.end = getelementptr inbounds i8, ptr %src, i32 %N.add.1.ext307 %cmp.src.start = icmp slt ptr %src, %lower308 %cmp.src.end = icmp sge ptr %src.end, %upper309 %or.precond.0 = or i1 %cmp.src.start, %cmp.src.end310 br i1 %or.precond.0, label %trap.bb, label %step.check311 312trap.bb:313 ret i4 2314 315step.check:316 %step.add.1 = add nuw nsw i16 %step, 1317 %step.add.1.ext = zext i16 %step.add.1 to i32318 %step.slt.N = icmp slt i32 %step.add.1.ext, %N.add.1.ext319 br i1 %step.slt.N, label %ptr.check, label %exit320 321ptr.check:322 %src.step = getelementptr inbounds i8, ptr %src, i32 %step.add.1.ext323 %cmp.step.start = icmp slt ptr %src.step, %lower324 %cmp.step.end = icmp sge ptr %src.step, %upper325 %or.check = or i1 %cmp.step.start, %cmp.step.end326 br i1 %or.check, label %trap.bb, label %exit327 328exit:329 ret i4 3330}331 332define i4 @ptr_N_step_zext_n_zext_out_of_bounds(ptr %src, ptr %lower, ptr %upper, i16 %N, i16 %step) {333; CHECK-LABEL: @ptr_N_step_zext_n_zext_out_of_bounds(334; CHECK-NEXT: entry:335; CHECK-NEXT: [[N_ADD_2:%.*]] = add nuw nsw i16 [[N:%.*]], 2336; CHECK-NEXT: [[N_ADD_2_EXT:%.*]] = zext i16 [[N_ADD_2]] to i32337; CHECK-NEXT: [[SRC_END:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i32 [[N_ADD_2_EXT]]338; CHECK-NEXT: [[CMP_SRC_START:%.*]] = icmp slt ptr [[SRC]], [[LOWER:%.*]]339; CHECK-NEXT: [[CMP_SRC_END:%.*]] = icmp sge ptr [[SRC_END]], [[UPPER:%.*]]340; CHECK-NEXT: [[OR_PRECOND_0:%.*]] = or i1 [[CMP_SRC_START]], [[CMP_SRC_END]]341; CHECK-NEXT: br i1 [[OR_PRECOND_0]], label [[TRAP_BB:%.*]], label [[STEP_CHECK:%.*]]342; CHECK: trap.bb:343; CHECK-NEXT: ret i4 2344; CHECK: step.check:345; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add nuw nsw i16 [[STEP:%.*]], 2346; CHECK-NEXT: [[STEP_ADD_2_EXT:%.*]] = zext i16 [[STEP_ADD_2]] to i32347; CHECK-NEXT: [[STEP_EXT:%.*]] = zext i16 [[STEP]] to i32348; CHECK-NEXT: [[STEP_SLT_N:%.*]] = icmp slt i32 [[STEP_EXT]], [[N_ADD_2_EXT]]349; CHECK-NEXT: br i1 [[STEP_SLT_N]], label [[PTR_CHECK:%.*]], label [[EXIT:%.*]]350; CHECK: ptr.check:351; CHECK-NEXT: [[SRC_STEP:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i32 [[STEP_ADD_2_EXT]]352; CHECK-NEXT: [[CMP_STEP_START:%.*]] = icmp slt ptr [[SRC_STEP]], [[LOWER]]353; CHECK-NEXT: [[CMP_STEP_END:%.*]] = icmp sge ptr [[SRC_STEP]], [[UPPER]]354; CHECK-NEXT: [[OR_CHECK:%.*]] = or i1 [[CMP_STEP_START]], [[CMP_STEP_END]]355; CHECK-NEXT: br i1 [[OR_CHECK]], label [[TRAP_BB]], label [[EXIT]]356; CHECK: exit:357; CHECK-NEXT: ret i4 3358;359entry:360 %N.add.2 = add nuw nsw i16 %N, 2361 %N.add.2.ext = zext i16 %N.add.2 to i32362 %src.end = getelementptr inbounds i8, ptr %src, i32 %N.add.2.ext363 %cmp.src.start = icmp slt ptr %src, %lower364 %cmp.src.end = icmp sge ptr %src.end, %upper365 %or.precond.0 = or i1 %cmp.src.start, %cmp.src.end366 br i1 %or.precond.0, label %trap.bb, label %step.check367 368trap.bb:369 ret i4 2370 371step.check:372 %step.add.2 = add nuw nsw i16 %step, 2373 %step.add.2.ext = zext i16 %step.add.2 to i32374 %step.ext = zext i16 %step to i32375 %step.slt.N = icmp slt i32 %step.ext, %N.add.2.ext376 br i1 %step.slt.N, label %ptr.check, label %exit377 378ptr.check:379 %src.step = getelementptr inbounds i8, ptr %src, i32 %step.add.2.ext380 %cmp.step.start = icmp slt ptr %src.step, %lower381 %cmp.step.end = icmp sge ptr %src.step, %upper382 %or.check = or i1 %cmp.step.start, %cmp.step.end383 br i1 %or.check, label %trap.bb, label %exit384 385exit:386 ret i4 3387}388 389define i1 @gep_count_add_1_sge_known_slt_1(i32 %count, ptr %p) {390; CHECK-LABEL: @gep_count_add_1_sge_known_slt_1(391; CHECK-NEXT: entry:392; CHECK-NEXT: [[SGE:%.*]] = icmp sge i32 [[COUNT:%.*]], 1393; CHECK-NEXT: call void @llvm.assume(i1 [[SGE]])394; CHECK-NEXT: [[COUNT_EXT:%.*]] = zext i32 [[COUNT]] to i64395; CHECK-NEXT: [[GEP_COUNT:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[COUNT_EXT]]396; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[COUNT]], -1397; CHECK-NEXT: [[SUB_EXT:%.*]] = zext i32 [[SUB]] to i64398; CHECK-NEXT: [[GEP_SUB:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 [[SUB_EXT]]399; CHECK-NEXT: [[C:%.*]] = icmp slt ptr [[GEP_SUB]], [[GEP_COUNT]]400; CHECK-NEXT: ret i1 [[C]]401;402entry:403 %sge = icmp sge i32 %count, 1404 call void @llvm.assume(i1 %sge)405 %count.ext = zext i32 %count to i64406 %gep.count = getelementptr inbounds i32, ptr %p, i64 %count.ext407 %sub = add nsw i32 %count, -1408 %sub.ext = zext i32 %sub to i64409 %gep.sub = getelementptr inbounds i32, ptr %p, i64 %sub.ext410 %c = icmp slt ptr %gep.sub, %gep.count411 ;%2 = icmp sge ptr %0, %p412 ret i1 %c413}414 415define i1 @gep_count_add_1_sge_known_sge_1(i32 %count, ptr %p) {416; CHECK-LABEL: @gep_count_add_1_sge_known_sge_1(417; CHECK-NEXT: entry:418; CHECK-NEXT: [[SGE:%.*]] = icmp sge i32 [[COUNT:%.*]], 1419; CHECK-NEXT: call void @llvm.assume(i1 [[SGE]])420; CHECK-NEXT: [[COUNT_EXT:%.*]] = zext i32 [[COUNT]] to i64421; CHECK-NEXT: [[GEP_COUNT:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[COUNT_EXT]]422; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[COUNT]], -1423; CHECK-NEXT: [[SUB_EXT:%.*]] = zext i32 [[SUB]] to i64424; CHECK-NEXT: [[GEP_SUB:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 [[SUB_EXT]]425; CHECK-NEXT: [[C:%.*]] = icmp sge ptr [[GEP_SUB]], [[P]]426; CHECK-NEXT: ret i1 [[C]]427;428entry:429 %sge = icmp sge i32 %count, 1430 call void @llvm.assume(i1 %sge)431 %count.ext = zext i32 %count to i64432 %gep.count = getelementptr inbounds i32, ptr %p, i64 %count.ext433 %sub = add nsw i32 %count, -1434 %sub.ext = zext i32 %sub to i64435 %gep.sub = getelementptr inbounds i32, ptr %p, i64 %sub.ext436 %c = icmp sge ptr %gep.sub, %p437 ret i1 %c438}439 440define i1 @gep_count_add_2_sge_not_known_slt_1(i32 %count, ptr %p) {441; CHECK-LABEL: @gep_count_add_2_sge_not_known_slt_1(442; CHECK-NEXT: entry:443; CHECK-NEXT: [[SGE:%.*]] = icmp sge i32 [[COUNT:%.*]], 1444; CHECK-NEXT: call void @llvm.assume(i1 [[SGE]])445; CHECK-NEXT: [[COUNT_EXT:%.*]] = zext i32 [[COUNT]] to i64446; CHECK-NEXT: [[GEP_COUNT:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[COUNT_EXT]]447; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[COUNT]], -2448; CHECK-NEXT: [[SUB_EXT:%.*]] = zext i32 [[SUB]] to i64449; CHECK-NEXT: [[GEP_SUB:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 [[SUB_EXT]]450; CHECK-NEXT: [[C:%.*]] = icmp slt ptr [[GEP_SUB]], [[GEP_COUNT]]451; CHECK-NEXT: ret i1 [[C]]452;453entry:454 %sge = icmp sge i32 %count, 1455 call void @llvm.assume(i1 %sge)456 %count.ext = zext i32 %count to i64457 %gep.count = getelementptr inbounds i32, ptr %p, i64 %count.ext458 %sub = add nsw i32 %count, -2459 %sub.ext = zext i32 %sub to i64460 %gep.sub = getelementptr inbounds i32, ptr %p, i64 %sub.ext461 %c = icmp slt ptr %gep.sub, %gep.count462 ret i1 %c463}464 465define i1 @gep_count_add_2_sge_not_known_sge_1(i32 %count, ptr %p) {466; CHECK-LABEL: @gep_count_add_2_sge_not_known_sge_1(467; CHECK-NEXT: entry:468; CHECK-NEXT: [[SGE:%.*]] = icmp sge i32 [[COUNT:%.*]], 1469; CHECK-NEXT: call void @llvm.assume(i1 [[SGE]])470; CHECK-NEXT: [[COUNT_EXT:%.*]] = zext i32 [[COUNT]] to i64471; CHECK-NEXT: [[GEP_COUNT:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[COUNT_EXT]]472; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[COUNT]], -2473; CHECK-NEXT: [[SUB_EXT:%.*]] = zext i32 [[SUB]] to i64474; CHECK-NEXT: [[GEP_SUB:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 [[SUB_EXT]]475; CHECK-NEXT: [[C:%.*]] = icmp sge ptr [[GEP_SUB]], [[P]]476; CHECK-NEXT: ret i1 [[C]]477;478entry:479 %sge = icmp sge i32 %count, 1480 call void @llvm.assume(i1 %sge)481 %count.ext = zext i32 %count to i64482 %gep.count = getelementptr inbounds i32, ptr %p, i64 %count.ext483 %sub = add nsw i32 %count, -2484 %sub.ext = zext i32 %sub to i64485 %gep.sub = getelementptr inbounds i32, ptr %p, i64 %sub.ext486 %c = icmp sge ptr %gep.sub, %p487 ret i1 %c488}489