63 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s3 4declare i64 @llvm.uadd.sat.i64(i64, i64)5declare i64 @llvm.usub.sat.i64(i64, i64)6 7define i1 @uadd_sat_uge(i64 noundef %a, i64 noundef %b) {8; CHECK-LABEL: define i1 @uadd_sat_uge(9; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) {10; CHECK-NEXT: [[ADD_SAT:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]])11; CHECK-NEXT: [[CMP:%.*]] = and i1 true, true12; CHECK-NEXT: ret i1 [[CMP]]13;14 %add.sat = call i64 @llvm.uadd.sat.i64(i64 %a, i64 %b)15 %cmp1 = icmp uge i64 %add.sat, %a16 %cmp2 = icmp uge i64 %add.sat, %b17 %cmp = and i1 %cmp1, %cmp218 ret i1 %cmp19}20 21define i1 @usub_sat_ule_lhs(i64 noundef %a, i64 noundef %b) {22; CHECK-LABEL: define i1 @usub_sat_ule_lhs(23; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) {24; CHECK-NEXT: [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])25; CHECK-NEXT: ret i1 true26;27 %sub.sat = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b)28 %cmp = icmp ule i64 %sub.sat, %a29 ret i1 %cmp30}31 32; Negative test33define i1 @usub_sat_not_ule_rhs(i64 noundef %a, i64 noundef %b) {34; CHECK-LABEL: define i1 @usub_sat_not_ule_rhs(35; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) {36; CHECK-NEXT: [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])37; CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[SUB_SAT]], [[B]]38; CHECK-NEXT: ret i1 [[CMP]]39;40 %sub.sat = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b)41 %cmp = icmp ule i64 %sub.sat, %b42 ret i1 %cmp43}44 45define i1 @pr135603(i64 %conv6, i64 %str.coerce, ptr %conv) {46; CHECK-LABEL: define i1 @pr135603(47; CHECK-SAME: i64 [[CONV6:%.*]], i64 [[STR_COERCE:%.*]], ptr [[CONV:%.*]]) {48; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[CONV]], align 449; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], -150; CHECK-NEXT: [[CONV2:%.*]] = zext nneg i32 [[A]] to i6451; CHECK-NEXT: [[ADD:%.*]] = add i64 [[STR_COERCE]], [[CONV6]]52; CHECK-NEXT: [[SPEC_SELECT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[CONV2]], i64 [[ADD]])53; CHECK-NEXT: ret i1 [[CMP]]54;55 %a = load i32, ptr %conv, align 456 %cmp = icmp sgt i32 %a, -157 %conv2 = zext nneg i32 %a to i6458 %add = add i64 %str.coerce, %conv659 %spec.select = call i64 @llvm.usub.sat.i64(i64 %conv2, i64 %add)60 ret i1 %cmp61}62 63