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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -S -mtriple=aarch64-none-linux-gnu -mattr=+neon -passes=early-cse -earlycse-debug-hash | FileCheck %s3; RUN: opt < %s -S -mtriple=aarch64-none-linux-gnu -mattr=+neon -aa-pipeline=basic-aa -passes='early-cse<memssa>' -verify-analysis-invalidation | FileCheck %s4 5define <4 x i32> @test_cse(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {6; CHECK-LABEL: define <4 x i32> @test_cse(7; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*]]:9; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 010; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 111; CHECK-NEXT: br label %[[FOR_COND:.*]]12; CHECK: [[FOR_COND]]:13; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]14; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]15; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]16; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]17; CHECK: [[FOR_BODY]]:18; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>19; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>20; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { <4 x i32>, <4 x i32> } poison, <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], 021; CHECK-NEXT: [[TMP3:%.*]] = insertvalue { <4 x i32>, <4 x i32> } [[TMP2]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], 122; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])23; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]])24; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 125; CHECK-NEXT: br label %[[FOR_COND]]26; CHECK: [[FOR_END]]:27; CHECK-NEXT: ret <4 x i32> [[RES_0]]28;29entry:30; Check that @llvm.aarch64.neon.ld2 is optimized away by Early CSE.31 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 032 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 133 br label %for.cond34 35for.cond: ; preds = %for.body, %entry36 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]37 %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]38 %cmp = icmp slt i32 %i.0, %n39 br i1 %cmp, label %for.body, label %for.end40 41for.body: ; preds = %for.cond42 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>43 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>44 %2 = bitcast <16 x i8> %0 to <4 x i32>45 %3 = bitcast <16 x i8> %1 to <4 x i32>46 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)47 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)48 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 049 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 150 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)51 %inc = add nsw i32 %i.0, 152 br label %for.cond53 54for.end: ; preds = %for.cond55 ret <4 x i32> %res.056}57 58define <4 x i32> @test_cse2(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {59; CHECK-LABEL: define <4 x i32> @test_cse2(60; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {61; CHECK-NEXT: [[ENTRY:.*]]:62; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 063; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 164; CHECK-NEXT: br label %[[FOR_COND:.*]]65; CHECK: [[FOR_COND]]:66; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]67; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]68; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]69; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]70; CHECK: [[FOR_BODY]]:71; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>72; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>73; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], ptr [[A]])74; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { <4 x i32>, <4 x i32> } poison, <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], 075; CHECK-NEXT: [[TMP3:%.*]] = insertvalue { <4 x i32>, <4 x i32> } [[TMP2]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], 176; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])77; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]])78; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 179; CHECK-NEXT: br label %[[FOR_COND]]80; CHECK: [[FOR_END]]:81; CHECK-NEXT: ret <4 x i32> [[RES_0]]82;83entry:84; Check that the first @llvm.aarch64.neon.st2 is optimized away by Early CSE.85 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 086 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 187 br label %for.cond88 89for.cond: ; preds = %for.body, %entry90 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]91 %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]92 %cmp = icmp slt i32 %i.0, %n93 br i1 %cmp, label %for.body, label %for.end94 95for.body: ; preds = %for.cond96 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>97 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>98 %2 = bitcast <16 x i8> %0 to <4 x i32>99 %3 = bitcast <16 x i8> %1 to <4 x i32>100 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %2, ptr %a)101 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)102 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)103 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0104 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1105 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)106 %inc = add nsw i32 %i.0, 1107 br label %for.cond108 109for.end: ; preds = %for.cond110 ret <4 x i32> %res.0111}112 113define <4 x i32> @test_cse3(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) #0 {114; CHECK-LABEL: define <4 x i32> @test_cse3(115; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {116; CHECK-NEXT: [[ENTRY:.*]]:117; CHECK-NEXT: br label %[[FOR_COND:.*]]118; CHECK: [[FOR_COND]]:119; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]120; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]121; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]122; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]123; CHECK: [[FOR_BODY]]:124; CHECK-NEXT: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr [[A]])125; CHECK-NEXT: [[VLD2_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2]], 0126; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD2_FCA_0_EXTRACT]], <4 x i32> [[VLD2_FCA_0_EXTRACT]])127; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1128; CHECK-NEXT: br label %[[FOR_COND]]129; CHECK: [[FOR_END]]:130; CHECK-NEXT: ret <4 x i32> [[RES_0]]131;132entry:133; Check that the first @llvm.aarch64.neon.ld2 is optimized away by Early CSE.134 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0135 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1136 br label %for.cond137 138for.cond: ; preds = %for.body, %entry139 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]140 %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]141 %cmp = icmp slt i32 %i.0, %n142 br i1 %cmp, label %for.body, label %for.end143 144for.body: ; preds = %for.cond145 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)146 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0147 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1148 %vld22 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)149 %vld22.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld22, 0150 %vld22.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld22, 1151 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld22.fca.0.extract)152 %inc = add nsw i32 %i.0, 1153 br label %for.cond154 155for.end: ; preds = %for.cond156 ret <4 x i32> %res.0157}158 159 160define <4 x i32> @test_nocse(ptr %a, ptr %b, [2 x <4 x i32>] %s.coerce, i32 %n) {161; CHECK-LABEL: define <4 x i32> @test_nocse(162; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {163; CHECK-NEXT: [[ENTRY:.*]]:164; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0165; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1166; CHECK-NEXT: br label %[[FOR_COND:.*]]167; CHECK: [[FOR_COND]]:168; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]169; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]170; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]171; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]172; CHECK: [[FOR_BODY]]:173; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>174; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>175; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])176; CHECK-NEXT: store i32 0, ptr [[B]], align 4177; CHECK-NEXT: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr [[A]])178; CHECK-NEXT: [[VLD2_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2]], 0179; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD2_FCA_0_EXTRACT]], <4 x i32> [[VLD2_FCA_0_EXTRACT]])180; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1181; CHECK-NEXT: br label %[[FOR_COND]]182; CHECK: [[FOR_END]]:183; CHECK-NEXT: ret <4 x i32> [[RES_0]]184;185entry:186; Check that the store prevents @llvm.aarch64.neon.ld2 from being optimized187; away by Early CSE.188 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0189 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1190 br label %for.cond191 192for.cond: ; preds = %for.body, %entry193 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]194 %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]195 %cmp = icmp slt i32 %i.0, %n196 br i1 %cmp, label %for.body, label %for.end197 198for.body: ; preds = %for.cond199 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>200 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>201 %2 = bitcast <16 x i8> %0 to <4 x i32>202 %3 = bitcast <16 x i8> %1 to <4 x i32>203 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)204 store i32 0, ptr %b, align 4205 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)206 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0207 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1208 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)209 %inc = add nsw i32 %i.0, 1210 br label %for.cond211 212for.end: ; preds = %for.cond213 ret <4 x i32> %res.0214}215 216define <4 x i32> @test_nocse2(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {217; CHECK-LABEL: define <4 x i32> @test_nocse2(218; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {219; CHECK-NEXT: [[ENTRY:.*]]:220; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0221; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1222; CHECK-NEXT: br label %[[FOR_COND:.*]]223; CHECK: [[FOR_COND]]:224; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]225; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]226; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]227; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]228; CHECK: [[FOR_BODY]]:229; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>230; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>231; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])232; CHECK-NEXT: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr [[A]])233; CHECK-NEXT: [[VLD3_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], 0234; CHECK-NEXT: [[VLD3_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], 2235; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD3_FCA_0_EXTRACT]], <4 x i32> [[VLD3_FCA_2_EXTRACT]])236; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1237; CHECK-NEXT: br label %[[FOR_COND]]238; CHECK: [[FOR_END]]:239; CHECK-NEXT: ret <4 x i32> [[RES_0]]240;241entry:242; Check that @llvm.aarch64.neon.ld3 is not optimized away by Early CSE due243; to mismatch between st2 and ld3.244 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0245 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1246 br label %for.cond247 248for.cond: ; preds = %for.body, %entry249 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]250 %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]251 %cmp = icmp slt i32 %i.0, %n252 br i1 %cmp, label %for.body, label %for.end253 254for.body: ; preds = %for.cond255 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>256 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>257 %2 = bitcast <16 x i8> %0 to <4 x i32>258 %3 = bitcast <16 x i8> %1 to <4 x i32>259 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)260 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %a)261 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0262 %vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2263 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)264 %inc = add nsw i32 %i.0, 1265 br label %for.cond266 267for.end: ; preds = %for.cond268 ret <4 x i32> %res.0269}270 271define <4 x i32> @test_nocse3(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {272; CHECK-LABEL: define <4 x i32> @test_nocse3(273; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {274; CHECK-NEXT: [[ENTRY:.*]]:275; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0276; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1277; CHECK-NEXT: br label %[[FOR_COND:.*]]278; CHECK: [[FOR_COND]]:279; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]280; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]281; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]282; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]283; CHECK: [[FOR_BODY]]:284; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>285; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>286; CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> [[S_COERCE_FCA_1_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], ptr [[A]])287; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], ptr [[A]])288; CHECK-NEXT: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr [[A]])289; CHECK-NEXT: [[VLD3_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], 0290; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD3_FCA_0_EXTRACT]], <4 x i32> [[VLD3_FCA_0_EXTRACT]])291; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1292; CHECK-NEXT: br label %[[FOR_COND]]293; CHECK: [[FOR_END]]:294; CHECK-NEXT: ret <4 x i32> [[RES_0]]295;296entry:297; Check that @llvm.aarch64.neon.st3 is not optimized away by Early CSE due to298; mismatch between st2 and st3.299 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0300 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1301 br label %for.cond302 303for.cond: ; preds = %for.body, %entry304 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]305 %res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]306 %cmp = icmp slt i32 %i.0, %n307 br i1 %cmp, label %for.body, label %for.end308 309for.body: ; preds = %for.cond310 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>311 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>312 %2 = bitcast <16 x i8> %0 to <4 x i32>313 %3 = bitcast <16 x i8> %1 to <4 x i32>314 call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %3, <4 x i32> %2, <4 x i32> %2, ptr %a)315 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %2, ptr %a)316 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %a)317 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0318 %vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1319 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)320 %inc = add nsw i32 %i.0, 1321 br label %for.cond322 323for.end: ; preds = %for.cond324 ret <4 x i32> %res.0325}326 327define void @test_ld4_st4_no_cse(ptr %p, <16 x i8> %A, <16 x i8> %B) {328; CHECK-LABEL: define void @test_ld4_st4_no_cse(329; CHECK-SAME: ptr [[P:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] {330; CHECK-NEXT: [[ENTRY:.*:]]331; CHECK-NEXT: [[LD:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0(ptr [[P]])332; CHECK-NEXT: [[EXT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[LD]], 0333; CHECK-NEXT: tail call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[EXT]], <16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> zeroinitializer, ptr [[P]])334; CHECK-NEXT: ret void335;336entry:337 %ld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0(ptr %p)338 %ext = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld, 0339 tail call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %ext, <16 x i8> %A, <16 x i8> %B, <16 x i8> zeroinitializer, ptr %p)340 ret void341}342 343; Function Attrs: nounwind344declare void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32>, <4 x i32>, ptr nocapture)345 346; Function Attrs: nounwind347declare void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, ptr nocapture)348 349; Function Attrs: nounwind readonly350declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr)351 352; Function Attrs: nounwind readonly353declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr)354 355define internal fastcc <4 x i32> @vaddq_s32(<4 x i32> %__p0, <4 x i32> %__p1) {356; CHECK-LABEL: define internal fastcc <4 x i32> @vaddq_s32(357; CHECK-SAME: <4 x i32> [[__P0:%.*]], <4 x i32> [[__P1:%.*]]) #[[ATTR0]] {358; CHECK-NEXT: [[ENTRY:.*:]]359; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[__P0]], [[__P1]]360; CHECK-NEXT: ret <4 x i32> [[ADD]]361;362entry:363 %add = add <4 x i32> %__p0, %__p1364 ret <4 x i32> %add365}366