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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt < %s -S -mtriple=amdgcn-- -passes=early-cse -earlycse-debug-hash | FileCheck %s3 4; Should not CSE calls marked as convergent, even if the callee is not convergent.5 6define i32 @test_read_register(i32 %cond) {7; CHECK-LABEL: define i32 @test_read_register8; CHECK-SAME: (i32 [[COND:%.*]]) {9; CHECK-NEXT: entry:10; CHECK-NEXT: [[X1:%.*]] = call i32 @llvm.read_register.i32(metadata [[META0:![0-9]+]]) #[[ATTR2:[0-9]+]]11; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[COND]], 012; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]13; CHECK: if:14; CHECK-NEXT: [[Y1:%.*]] = call i32 @llvm.read_register.i32(metadata [[META0]]) #[[ATTR2]]15; CHECK-NEXT: br label [[END]]16; CHECK: end:17; CHECK-NEXT: [[Y2:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[Y1]], [[IF]] ]18; CHECK-NEXT: [[RET:%.*]] = add i32 [[X1]], [[Y2]]19; CHECK-NEXT: ret i32 [[RET]]20;21entry:22 ; %x = ballot operation over all lanes.23 %x1 = call i32 @llvm.read_register.i32(metadata !{!"exec_lo"}) convergent24 %cmp = icmp eq i32 %cond, 025 br i1 %cmp, label %if, label %end26 27if:28 ; %y = ballot operation over lanes satisfying %cond.29 %y1 = call i32 @llvm.read_register.i32(metadata !{!"exec_lo"}) convergent30 br label %end31 32end:33 %y2 = phi i32 [0, %entry], [%y1, %if]34 %ret = add i32 %x1, %y235 ret i32 %ret36}37 38define i32 @test_read_register_samebb(i32 %cond) {39; CHECK-LABEL: define i32 @test_read_register_samebb40; CHECK-SAME: (i32 [[COND:%.*]]) {41; CHECK-NEXT: entry:42; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.read_register.i32(metadata [[META0]]) #[[ATTR2]]43; CHECK-NEXT: [[RET:%.*]] = add i32 [[X]], [[X]]44; CHECK-NEXT: ret i32 [[RET]]45;46entry:47 %x = call i32 @llvm.read_register.i32(metadata !{!"exec_lo"}) convergent48 %y = call i32 @llvm.read_register.i32(metadata !{!"exec_lo"}) convergent49 %ret = add i32 %x, %y50 ret i32 %ret51}52 53define i1 @test_live_mask(i32 %cond) {54; CHECK-LABEL: define i1 @test_live_mask55; CHECK-SAME: (i32 [[COND:%.*]]) {56; CHECK-NEXT: entry:57; CHECK-NEXT: [[X1:%.*]] = call i1 @llvm.amdgcn.live.mask() #[[ATTR2]]58; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[COND]], 059; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]60; CHECK: if:61; CHECK-NEXT: [[Y1:%.*]] = call i1 @llvm.amdgcn.live.mask() #[[ATTR2]]62; CHECK-NEXT: br label [[END]]63; CHECK: end:64; CHECK-NEXT: [[Y2:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[Y1]], [[IF]] ]65; CHECK-NEXT: [[RET:%.*]] = add i1 [[X1]], [[Y2]]66; CHECK-NEXT: ret i1 [[RET]]67;68entry:69 %x1 = call i1 @llvm.amdgcn.live.mask() convergent70 %cmp = icmp eq i32 %cond, 071 br i1 %cmp, label %if, label %end72 73if:74 %y1 = call i1 @llvm.amdgcn.live.mask() convergent75 br label %end76 77end:78 %y2 = phi i1 [0, %entry], [%y1, %if]79 %ret = add i1 %x1, %y280 ret i1 %ret81}82 83declare i32 @llvm.read_register.i32(metadata)84declare i1 @llvm.amdgcn.live.mask()85