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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -passes=early-cse -earlycse-debug-hash < %s | FileCheck %s3; NOTE: This file is testing the current implementation. Some of4; the transforms used as negative tests below would be legal, but5; only if reached through a chain of logic which EarlyCSE is incapable6; of performing. To say it differently, this file tests a conservative7; version of the memory model. If we want to extend EarlyCSE to be more8; aggressive in the future, we may need to relax some of the negative tests.9 10; We can value forward across the fence since we can (semantically)11; reorder the following load before the fence.12define i32 @test(ptr %addr.i) {13; CHECK-LABEL: define i32 @test14; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {15; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 416; CHECK-NEXT: fence release17; CHECK-NEXT: ret i32 518;19 store i32 5, ptr %addr.i, align 420 fence release21 %a = load i32, ptr %addr.i, align 422 ret i32 %a23}24 25; Same as above26define i32 @test2(ptr noalias %addr.i, ptr noalias %otheraddr) {27; CHECK-LABEL: define i32 @test228; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {29; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[ADDR_I]], align 430; CHECK-NEXT: fence release31; CHECK-NEXT: ret i32 [[A]]32;33 %a = load i32, ptr %addr.i, align 434 fence release35 %a2 = load i32, ptr %addr.i, align 436 %res = sub i32 %a, %a237 ret i32 %a38}39 40; We can not value forward across an acquire barrier since we might41; be syncronizing with another thread storing to the same variable42; followed by a release fence. If this thread observed the release43; had happened, we must present a consistent view of memory at the44; fence. Note that it would be legal to reorder '%a' after the fence45; and then remove '%a2'. The current implementation doesn't know how46; to do this, but if it learned, this test will need revised.47define i32 @test3(ptr noalias %addr.i, ptr noalias %otheraddr) {48; CHECK-LABEL: define i32 @test349; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {50; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[ADDR_I]], align 451; CHECK-NEXT: fence acquire52; CHECK-NEXT: [[A2:%.*]] = load i32, ptr [[ADDR_I]], align 453; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[A2]]54; CHECK-NEXT: ret i32 [[RES]]55;56 %a = load i32, ptr %addr.i, align 457 fence acquire58 %a2 = load i32, ptr %addr.i, align 459 %res = sub i32 %a, %a260 ret i32 %res61}62 63; We can not dead store eliminate accross the fence. We could in64; principal reorder the second store above the fence and then DSE either65; store, but this is beyond the simple last-store DSE which EarlyCSE66; implements.67define void @test4(ptr %addr.i) {68; CHECK-LABEL: define void @test469; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {70; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 471; CHECK-NEXT: fence release72; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 473; CHECK-NEXT: ret void74;75 store i32 5, ptr %addr.i, align 476 fence release77 store i32 5, ptr %addr.i, align 478 ret void79}80 81; We *could* DSE across this fence, but don't. No other thread can82; observe the order of the acquire fence and the store.83define void @test5(ptr %addr.i) {84; CHECK-LABEL: define void @test585; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {86; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 487; CHECK-NEXT: fence acquire88; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 489; CHECK-NEXT: ret void90;91 store i32 5, ptr %addr.i, align 492 fence acquire93 store i32 5, ptr %addr.i, align 494 ret void95}96