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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn -passes="expand-fp<O1>" %s -S -o - | FileCheck %s3 4define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,5; CHECK-LABEL: define amdgpu_kernel void @frem_f16(6; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {7; CHECK-NEXT: [[GEP2:%.*]] = getelementptr half, ptr addrspace(1) [[IN2]], i32 48; CHECK-NEXT: [[R0:%.*]] = load half, ptr addrspace(1) [[IN1]], align 49; CHECK-NEXT: [[R1:%.*]] = load half, ptr addrspace(1) [[GEP2]], align 410; CHECK-NEXT: [[AX:%.*]] = call half @llvm.fabs.f16(half [[R0]])11; CHECK-NEXT: [[AY:%.*]] = call half @llvm.fabs.f16(half [[R1]])12; CHECK-NEXT: [[AX1:%.*]] = fpext half [[AX]] to float13; CHECK-NEXT: [[AY2:%.*]] = fpext half [[AY]] to float14; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt float [[AX1]], [[AY2]]15; CHECK-NEXT: br i1 [[TMP1]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]16; CHECK: [[BB2:.*]]:17; CHECK-NEXT: [[RET:%.*]] = phi half [ [[TMP25:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP16:%.*]], %[[FREM_ELSE]] ]18; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[R1]], 0xH000019; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], half 0xH7E00, half [[RET]]20; CHECK-NEXT: [[TMP5:%.*]] = call half @llvm.fabs.f16(half [[R0]])21; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult half [[TMP5]], 0xH7C0022; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], half [[TMP4]], half 0xH7E0023; CHECK-NEXT: store half [[R2]], ptr addrspace(1) [[OUT]], align 424; CHECK-NEXT: ret void25; CHECK: [[FREM_COMPUTE]]:26; CHECK-NEXT: [[TMP7:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX1]])27; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { float, i32 } [[TMP7]], 028; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { float, i32 } [[TMP7]], 129; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP9]], 130; CHECK-NEXT: [[AX3:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP8]], i32 11)31; CHECK-NEXT: [[TMP10:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY2]])32; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { float, i32 } [[TMP10]], 033; CHECK-NEXT: [[TMP12:%.*]] = extractvalue { float, i32 } [[TMP10]], 134; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP12]], 135; CHECK-NEXT: [[AY4:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP11]], i32 1)36; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]37; CHECK-NEXT: [[AYINV:%.*]] = fdiv float 1.000000e+00, [[AY4]]38; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[NB]], 1139; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]40; CHECK: [[FREM_ELSE]]:41; CHECK-NEXT: [[TMP14:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[R0]])42; CHECK-NEXT: [[TMP15:%.*]] = fcmp oeq float [[AX1]], [[AY2]]43; CHECK-NEXT: [[TMP16]] = select i1 [[TMP15]], half [[TMP14]], half [[R0]]44; CHECK-NEXT: br label %[[BB2]]45; CHECK: [[FREM_LOOP_BODY]]:46; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]47; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi float [ [[AX3]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]48; CHECK-NEXT: [[TMP17:%.*]] = fmul float [[AX_LOOP_PHI]], [[AYINV]]49; CHECK-NEXT: [[Q:%.*]] = call float @llvm.rint.f32(float [[TMP17]])50; CHECK-NEXT: [[TMP18:%.*]] = fneg float [[Q]]51; CHECK-NEXT: [[AX5:%.*]] = call float @llvm.fma.f32(float [[TMP18]], float [[AY4]], float [[AX_LOOP_PHI]])52; CHECK-NEXT: [[CLT:%.*]] = fcmp olt float [[AX5]], 0.000000e+0053; CHECK-NEXT: [[AXP:%.*]] = fadd float [[AX5]], [[AY4]]54; CHECK-NEXT: [[AX6:%.*]] = select i1 [[CLT]], float [[AXP]], float [[AX5]]55; CHECK-NEXT: [[AX_UPDATE]] = call float @llvm.ldexp.f32.i32(float [[AX6]], i32 11)56; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 1157; CHECK-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[NB_IV]], 1158; CHECK-NEXT: br i1 [[TMP19]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]59; CHECK: [[FREM_LOOP_EXIT]]:60; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi float [ [[AX3]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]61; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]62; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[NB_EXIT_PHI]], 1163; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 164; CHECK-NEXT: [[AX7:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI]], i32 [[TMP21]])65; CHECK-NEXT: [[TMP22:%.*]] = fmul float [[AX7]], [[AYINV]]66; CHECK-NEXT: [[Q8:%.*]] = call float @llvm.rint.f32(float [[TMP22]])67; CHECK-NEXT: [[TMP23:%.*]] = fneg float [[Q8]]68; CHECK-NEXT: [[AX9:%.*]] = call float @llvm.fma.f32(float [[TMP23]], float [[AY4]], float [[AX7]])69; CHECK-NEXT: [[CLT10:%.*]] = fcmp olt float [[AX9]], 0.000000e+0070; CHECK-NEXT: [[AXP11:%.*]] = fadd float [[AX9]], [[AY4]]71; CHECK-NEXT: [[AX12:%.*]] = select i1 [[CLT10]], float [[AXP11]], float [[AX9]]72; CHECK-NEXT: [[AX13:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX12]], i32 [[EY]])73; CHECK-NEXT: [[TMP24:%.*]] = fptrunc float [[AX13]] to half74; CHECK-NEXT: [[TMP25]] = call half @llvm.copysign.f16(half [[TMP24]], half [[R0]])75; CHECK-NEXT: br label %[[BB2]]76;77 ptr addrspace(1) %in2) {78 %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 479 %r0 = load half, ptr addrspace(1) %in1, align 480 %r1 = load half, ptr addrspace(1) %gep2, align 481 %r2 = frem half %r0, %r182 store half %r2, ptr addrspace(1) %out, align 483 ret void84}85 86define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,87; CHECK-LABEL: define amdgpu_kernel void @fast_frem_f16(88; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {89; CHECK-NEXT: [[GEP2:%.*]] = getelementptr half, ptr addrspace(1) [[IN2]], i32 490; CHECK-NEXT: [[R0:%.*]] = load half, ptr addrspace(1) [[IN1]], align 491; CHECK-NEXT: [[R1:%.*]] = load half, ptr addrspace(1) [[GEP2]], align 492; CHECK-NEXT: [[TMP1:%.*]] = fdiv half [[R0]], [[R1]]93; CHECK-NEXT: [[TMP2:%.*]] = call half @llvm.trunc.f16(half [[TMP1]])94; CHECK-NEXT: [[TMP3:%.*]] = fneg half [[TMP2]]95; CHECK-NEXT: [[R2:%.*]] = call half @llvm.fma.f16(half [[TMP3]], half [[R1]], half [[R0]])96; CHECK-NEXT: store half [[R2]], ptr addrspace(1) [[OUT]], align 497; CHECK-NEXT: ret void98;99 ptr addrspace(1) %in2) {100 %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4101 %r0 = load half, ptr addrspace(1) %in1, align 4102 %r1 = load half, ptr addrspace(1) %gep2, align 4103 %r2 = frem fast half %r0, %r1104 store half %r2, ptr addrspace(1) %out, align 4105 ret void106}107 108define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,109; CHECK-LABEL: define amdgpu_kernel void @unsafe_frem_f16(110; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {111; CHECK-NEXT: [[GEP2:%.*]] = getelementptr half, ptr addrspace(1) [[IN2]], i32 4112; CHECK-NEXT: [[R0:%.*]] = load half, ptr addrspace(1) [[IN1]], align 4113; CHECK-NEXT: [[R1:%.*]] = load half, ptr addrspace(1) [[GEP2]], align 4114; CHECK-NEXT: [[TMP1:%.*]] = fdiv half [[R0]], [[R1]]115; CHECK-NEXT: [[TMP2:%.*]] = call half @llvm.trunc.f16(half [[TMP1]])116; CHECK-NEXT: [[TMP3:%.*]] = fneg half [[TMP2]]117; CHECK-NEXT: [[R2:%.*]] = call half @llvm.fma.f16(half [[TMP3]], half [[R1]], half [[R0]])118; CHECK-NEXT: store half [[R2]], ptr addrspace(1) [[OUT]], align 4119; CHECK-NEXT: ret void120;121 ptr addrspace(1) %in2) {122 %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4123 %r0 = load half, ptr addrspace(1) %in1, align 4124 %r1 = load half, ptr addrspace(1) %gep2, align 4125 %r2 = frem afn half %r0, %r1126 store half %r2, ptr addrspace(1) %out, align 4127 ret void128}129 130define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,131; CHECK-LABEL: define amdgpu_kernel void @frem_f32(132; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {133; CHECK-NEXT: [[GEP2:%.*]] = getelementptr float, ptr addrspace(1) [[IN2]], i32 4134; CHECK-NEXT: [[R0:%.*]] = load float, ptr addrspace(1) [[IN1]], align 4135; CHECK-NEXT: [[R1:%.*]] = load float, ptr addrspace(1) [[GEP2]], align 4136; CHECK-NEXT: [[AX:%.*]] = call float @llvm.fabs.f32(float [[R0]])137; CHECK-NEXT: [[AY:%.*]] = call float @llvm.fabs.f32(float [[R1]])138; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt float [[AX]], [[AY]]139; CHECK-NEXT: br i1 [[TMP1]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]140; CHECK: [[BB2:.*]]:141; CHECK-NEXT: [[RET:%.*]] = phi float [ [[TMP24:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP16:%.*]], %[[FREM_ELSE]] ]142; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq float [[R1]], 0.000000e+00143; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], float 0x7FF8000000000000, float [[RET]]144; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.fabs.f32(float [[R0]])145; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult float [[TMP5]], 0x7FF0000000000000146; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], float [[TMP4]], float 0x7FF8000000000000147; CHECK-NEXT: store float [[R2]], ptr addrspace(1) [[OUT]], align 4148; CHECK-NEXT: ret void149; CHECK: [[FREM_COMPUTE]]:150; CHECK-NEXT: [[TMP7:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX]])151; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { float, i32 } [[TMP7]], 0152; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { float, i32 } [[TMP7]], 1153; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP9]], 1154; CHECK-NEXT: [[AX1:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP8]], i32 12)155; CHECK-NEXT: [[TMP10:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY]])156; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { float, i32 } [[TMP10]], 0157; CHECK-NEXT: [[TMP12:%.*]] = extractvalue { float, i32 } [[TMP10]], 1158; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP12]], 1159; CHECK-NEXT: [[AY2:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP11]], i32 1)160; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]161; CHECK-NEXT: [[AYINV:%.*]] = fdiv float 1.000000e+00, [[AY2]]162; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[NB]], 12163; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]164; CHECK: [[FREM_ELSE]]:165; CHECK-NEXT: [[TMP14:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[R0]])166; CHECK-NEXT: [[TMP15:%.*]] = fcmp oeq float [[AX]], [[AY]]167; CHECK-NEXT: [[TMP16]] = select i1 [[TMP15]], float [[TMP14]], float [[R0]]168; CHECK-NEXT: br label %[[BB2]]169; CHECK: [[FREM_LOOP_BODY]]:170; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]171; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi float [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]172; CHECK-NEXT: [[TMP17:%.*]] = fmul float [[AX_LOOP_PHI]], [[AYINV]]173; CHECK-NEXT: [[Q:%.*]] = call float @llvm.rint.f32(float [[TMP17]])174; CHECK-NEXT: [[TMP18:%.*]] = fneg float [[Q]]175; CHECK-NEXT: [[AX3:%.*]] = call float @llvm.fma.f32(float [[TMP18]], float [[AY2]], float [[AX_LOOP_PHI]])176; CHECK-NEXT: [[CLT:%.*]] = fcmp olt float [[AX3]], 0.000000e+00177; CHECK-NEXT: [[AXP:%.*]] = fadd float [[AX3]], [[AY2]]178; CHECK-NEXT: [[AX4:%.*]] = select i1 [[CLT]], float [[AXP]], float [[AX3]]179; CHECK-NEXT: [[AX_UPDATE]] = call float @llvm.ldexp.f32.i32(float [[AX4]], i32 12)180; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 12181; CHECK-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[NB_IV]], 12182; CHECK-NEXT: br i1 [[TMP19]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]183; CHECK: [[FREM_LOOP_EXIT]]:184; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi float [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]185; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]186; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[NB_EXIT_PHI]], 12187; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 1188; CHECK-NEXT: [[AX5:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI]], i32 [[TMP21]])189; CHECK-NEXT: [[TMP22:%.*]] = fmul float [[AX5]], [[AYINV]]190; CHECK-NEXT: [[Q6:%.*]] = call float @llvm.rint.f32(float [[TMP22]])191; CHECK-NEXT: [[TMP23:%.*]] = fneg float [[Q6]]192; CHECK-NEXT: [[AX7:%.*]] = call float @llvm.fma.f32(float [[TMP23]], float [[AY2]], float [[AX5]])193; CHECK-NEXT: [[CLT8:%.*]] = fcmp olt float [[AX7]], 0.000000e+00194; CHECK-NEXT: [[AXP9:%.*]] = fadd float [[AX7]], [[AY2]]195; CHECK-NEXT: [[AX10:%.*]] = select i1 [[CLT8]], float [[AXP9]], float [[AX7]]196; CHECK-NEXT: [[AX11:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX10]], i32 [[EY]])197; CHECK-NEXT: [[TMP24]] = call float @llvm.copysign.f32(float [[AX11]], float [[R0]])198; CHECK-NEXT: br label %[[BB2]]199;200 ptr addrspace(1) %in2) {201 %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4202 %r0 = load float, ptr addrspace(1) %in1, align 4203 %r1 = load float, ptr addrspace(1) %gep2, align 4204 %r2 = frem float %r0, %r1205 store float %r2, ptr addrspace(1) %out, align 4206 ret void207}208 209define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,210; CHECK-LABEL: define amdgpu_kernel void @fast_frem_f32(211; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {212; CHECK-NEXT: [[GEP2:%.*]] = getelementptr float, ptr addrspace(1) [[IN2]], i32 4213; CHECK-NEXT: [[R0:%.*]] = load float, ptr addrspace(1) [[IN1]], align 4214; CHECK-NEXT: [[R1:%.*]] = load float, ptr addrspace(1) [[GEP2]], align 4215; CHECK-NEXT: [[TMP1:%.*]] = fdiv float [[R0]], [[R1]]216; CHECK-NEXT: [[TMP2:%.*]] = call float @llvm.trunc.f32(float [[TMP1]])217; CHECK-NEXT: [[TMP3:%.*]] = fneg float [[TMP2]]218; CHECK-NEXT: [[R2:%.*]] = call float @llvm.fma.f32(float [[TMP3]], float [[R1]], float [[R0]])219; CHECK-NEXT: store float [[R2]], ptr addrspace(1) [[OUT]], align 4220; CHECK-NEXT: ret void221;222 ptr addrspace(1) %in2) {223 %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4224 %r0 = load float, ptr addrspace(1) %in1, align 4225 %r1 = load float, ptr addrspace(1) %gep2, align 4226 %r2 = frem fast float %r0, %r1227 store float %r2, ptr addrspace(1) %out, align 4228 ret void229}230 231define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,232; CHECK-LABEL: define amdgpu_kernel void @unsafe_frem_f32(233; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {234; CHECK-NEXT: [[GEP2:%.*]] = getelementptr float, ptr addrspace(1) [[IN2]], i32 4235; CHECK-NEXT: [[R0:%.*]] = load float, ptr addrspace(1) [[IN1]], align 4236; CHECK-NEXT: [[R1:%.*]] = load float, ptr addrspace(1) [[GEP2]], align 4237; CHECK-NEXT: [[TMP1:%.*]] = fdiv float [[R0]], [[R1]]238; CHECK-NEXT: [[TMP2:%.*]] = call float @llvm.trunc.f32(float [[TMP1]])239; CHECK-NEXT: [[TMP3:%.*]] = fneg float [[TMP2]]240; CHECK-NEXT: [[R2:%.*]] = call float @llvm.fma.f32(float [[TMP3]], float [[R1]], float [[R0]])241; CHECK-NEXT: store float [[R2]], ptr addrspace(1) [[OUT]], align 4242; CHECK-NEXT: ret void243;244 ptr addrspace(1) %in2) {245 %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4246 %r0 = load float, ptr addrspace(1) %in1, align 4247 %r1 = load float, ptr addrspace(1) %gep2, align 4248 %r2 = frem afn float %r0, %r1249 store float %r2, ptr addrspace(1) %out, align 4250 ret void251}252 253define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,254; CHECK-LABEL: define amdgpu_kernel void @frem_f64(255; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {256; CHECK-NEXT: [[R0:%.*]] = load double, ptr addrspace(1) [[IN1]], align 8257; CHECK-NEXT: [[R1:%.*]] = load double, ptr addrspace(1) [[IN2]], align 8258; CHECK-NEXT: [[AX:%.*]] = call double @llvm.fabs.f64(double [[R0]])259; CHECK-NEXT: [[AY:%.*]] = call double @llvm.fabs.f64(double [[R1]])260; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt double [[AX]], [[AY]]261; CHECK-NEXT: br i1 [[TMP1]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]262; CHECK: [[BB2:.*]]:263; CHECK-NEXT: [[RET:%.*]] = phi double [ [[TMP24:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP16:%.*]], %[[FREM_ELSE]] ]264; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq double [[R1]], 0.000000e+00265; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], double 0x7FF8000000000000, double [[RET]]266; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.fabs.f64(double [[R0]])267; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult double [[TMP5]], 0x7FF0000000000000268; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], double [[TMP4]], double 0x7FF8000000000000269; CHECK-NEXT: store double [[R2]], ptr addrspace(1) [[OUT]], align 8270; CHECK-NEXT: ret void271; CHECK: [[FREM_COMPUTE]]:272; CHECK-NEXT: [[TMP7:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[AX]])273; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { double, i32 } [[TMP7]], 0274; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { double, i32 } [[TMP7]], 1275; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP9]], 1276; CHECK-NEXT: [[AX1:%.*]] = call double @llvm.ldexp.f64.i32(double [[TMP8]], i32 26)277; CHECK-NEXT: [[TMP10:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[AY]])278; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { double, i32 } [[TMP10]], 0279; CHECK-NEXT: [[TMP12:%.*]] = extractvalue { double, i32 } [[TMP10]], 1280; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP12]], 1281; CHECK-NEXT: [[AY2:%.*]] = call double @llvm.ldexp.f64.i32(double [[TMP11]], i32 1)282; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]283; CHECK-NEXT: [[AYINV:%.*]] = fdiv double 1.000000e+00, [[AY2]]284; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[NB]], 26285; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]286; CHECK: [[FREM_ELSE]]:287; CHECK-NEXT: [[TMP14:%.*]] = call double @llvm.copysign.f64(double 0.000000e+00, double [[R0]])288; CHECK-NEXT: [[TMP15:%.*]] = fcmp oeq double [[AX]], [[AY]]289; CHECK-NEXT: [[TMP16]] = select i1 [[TMP15]], double [[TMP14]], double [[R0]]290; CHECK-NEXT: br label %[[BB2]]291; CHECK: [[FREM_LOOP_BODY]]:292; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]293; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi double [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]294; CHECK-NEXT: [[TMP17:%.*]] = fmul double [[AX_LOOP_PHI]], [[AYINV]]295; CHECK-NEXT: [[Q:%.*]] = call double @llvm.rint.f64(double [[TMP17]])296; CHECK-NEXT: [[TMP18:%.*]] = fneg double [[Q]]297; CHECK-NEXT: [[AX3:%.*]] = call double @llvm.fma.f64(double [[TMP18]], double [[AY2]], double [[AX_LOOP_PHI]])298; CHECK-NEXT: [[CLT:%.*]] = fcmp olt double [[AX3]], 0.000000e+00299; CHECK-NEXT: [[AXP:%.*]] = fadd double [[AX3]], [[AY2]]300; CHECK-NEXT: [[AX4:%.*]] = select i1 [[CLT]], double [[AXP]], double [[AX3]]301; CHECK-NEXT: [[AX_UPDATE]] = call double @llvm.ldexp.f64.i32(double [[AX4]], i32 26)302; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 26303; CHECK-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[NB_IV]], 26304; CHECK-NEXT: br i1 [[TMP19]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]305; CHECK: [[FREM_LOOP_EXIT]]:306; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi double [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]307; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]308; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[NB_EXIT_PHI]], 26309; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 1310; CHECK-NEXT: [[AX5:%.*]] = call double @llvm.ldexp.f64.i32(double [[AX_EXIT_PHI]], i32 [[TMP21]])311; CHECK-NEXT: [[TMP22:%.*]] = fmul double [[AX5]], [[AYINV]]312; CHECK-NEXT: [[Q6:%.*]] = call double @llvm.rint.f64(double [[TMP22]])313; CHECK-NEXT: [[TMP23:%.*]] = fneg double [[Q6]]314; CHECK-NEXT: [[AX7:%.*]] = call double @llvm.fma.f64(double [[TMP23]], double [[AY2]], double [[AX5]])315; CHECK-NEXT: [[CLT8:%.*]] = fcmp olt double [[AX7]], 0.000000e+00316; CHECK-NEXT: [[AXP9:%.*]] = fadd double [[AX7]], [[AY2]]317; CHECK-NEXT: [[AX10:%.*]] = select i1 [[CLT8]], double [[AXP9]], double [[AX7]]318; CHECK-NEXT: [[AX11:%.*]] = call double @llvm.ldexp.f64.i32(double [[AX10]], i32 [[EY]])319; CHECK-NEXT: [[TMP24]] = call double @llvm.copysign.f64(double [[AX11]], double [[R0]])320; CHECK-NEXT: br label %[[BB2]]321;322 ptr addrspace(1) %in2) {323 %r0 = load double, ptr addrspace(1) %in1, align 8324 %r1 = load double, ptr addrspace(1) %in2, align 8325 %r2 = frem double %r0, %r1326 store double %r2, ptr addrspace(1) %out, align 8327 ret void328}329 330define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,331; CHECK-LABEL: define amdgpu_kernel void @fast_frem_f64(332; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {333; CHECK-NEXT: [[R0:%.*]] = load double, ptr addrspace(1) [[IN1]], align 8334; CHECK-NEXT: [[R1:%.*]] = load double, ptr addrspace(1) [[IN2]], align 8335; CHECK-NEXT: [[TMP1:%.*]] = fdiv double [[R0]], [[R1]]336; CHECK-NEXT: [[TMP2:%.*]] = call double @llvm.trunc.f64(double [[TMP1]])337; CHECK-NEXT: [[TMP3:%.*]] = fneg double [[TMP2]]338; CHECK-NEXT: [[R2:%.*]] = call double @llvm.fma.f64(double [[TMP3]], double [[R1]], double [[R0]])339; CHECK-NEXT: store double [[R2]], ptr addrspace(1) [[OUT]], align 8340; CHECK-NEXT: ret void341;342 ptr addrspace(1) %in2) {343 %r0 = load double, ptr addrspace(1) %in1, align 8344 %r1 = load double, ptr addrspace(1) %in2, align 8345 %r2 = frem fast double %r0, %r1346 store double %r2, ptr addrspace(1) %out, align 8347 ret void348}349 350define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,351; CHECK-LABEL: define amdgpu_kernel void @unsafe_frem_f64(352; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {353; CHECK-NEXT: [[R0:%.*]] = load double, ptr addrspace(1) [[IN1]], align 8354; CHECK-NEXT: [[R1:%.*]] = load double, ptr addrspace(1) [[IN2]], align 8355; CHECK-NEXT: [[TMP1:%.*]] = fdiv double [[R0]], [[R1]]356; CHECK-NEXT: [[TMP2:%.*]] = call double @llvm.trunc.f64(double [[TMP1]])357; CHECK-NEXT: [[TMP3:%.*]] = fneg double [[TMP2]]358; CHECK-NEXT: [[R2:%.*]] = call double @llvm.fma.f64(double [[TMP3]], double [[R1]], double [[R0]])359; CHECK-NEXT: store double [[R2]], ptr addrspace(1) [[OUT]], align 8360; CHECK-NEXT: ret void361;362 ptr addrspace(1) %in2) {363 %r0 = load double, ptr addrspace(1) %in1, align 8364 %r1 = load double, ptr addrspace(1) %in2, align 8365 %r2 = frem afn double %r0, %r1366 store double %r2, ptr addrspace(1) %out, align 8367 ret void368}369 370define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,371; CHECK-LABEL: define amdgpu_kernel void @frem_v2f16(372; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {373; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <2 x half>, ptr addrspace(1) [[IN2]], i32 4374; CHECK-NEXT: [[R0:%.*]] = load <2 x half>, ptr addrspace(1) [[IN1]], align 8375; CHECK-NEXT: [[R1:%.*]] = load <2 x half>, ptr addrspace(1) [[GEP2]], align 8376; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x half> [[R0]], i64 0377; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x half> [[R1]], i64 0378; CHECK-NEXT: [[AX:%.*]] = call half @llvm.fabs.f16(half [[TMP1]])379; CHECK-NEXT: [[AY:%.*]] = call half @llvm.fabs.f16(half [[TMP2]])380; CHECK-NEXT: [[AX1:%.*]] = fpext half [[AX]] to float381; CHECK-NEXT: [[AY2:%.*]] = fpext half [[AY]] to float382; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt float [[AX1]], [[AY2]]383; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE19:.*]], label %[[FREM_ELSE20:.*]]384; CHECK: [[BB4:.*]]:385; CHECK-NEXT: [[RET:%.*]] = phi half [ [[TMP58:%.*]], %[[FREM_LOOP_EXIT28:.*]] ], [ [[TMP57:%.*]], %[[FREM_ELSE20]] ]386; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq half [[TMP2]], 0xH0000387; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], half 0xH7E00, half [[RET]]388; CHECK-NEXT: [[TMP7:%.*]] = call half @llvm.fabs.f16(half [[TMP1]])389; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult half [[TMP7]], 0xH7C00390; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], half [[TMP6]], half 0xH7E00391; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x half> poison, half [[TMP9]], i64 0392; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x half> [[R0]], i64 1393; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x half> [[R1]], i64 1394; CHECK-NEXT: [[AX14:%.*]] = call half @llvm.fabs.f16(half [[TMP11]])395; CHECK-NEXT: [[AY15:%.*]] = call half @llvm.fabs.f16(half [[TMP12]])396; CHECK-NEXT: [[AX16:%.*]] = fpext half [[AX14]] to float397; CHECK-NEXT: [[AY17:%.*]] = fpext half [[AY15]] to float398; CHECK-NEXT: [[TMP13:%.*]] = fcmp ogt float [[AX16]], [[AY17]]399; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]400; CHECK: [[BB14:.*]]:401; CHECK-NEXT: [[RET18:%.*]] = phi half [ [[TMP46:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP38:%.*]], %[[FREM_ELSE]] ]402; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq half [[TMP12]], 0xH0000403; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], half 0xH7E00, half [[RET18]]404; CHECK-NEXT: [[TMP17:%.*]] = call half @llvm.fabs.f16(half [[TMP11]])405; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult half [[TMP17]], 0xH7C00406; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], half [[TMP16]], half 0xH7E00407; CHECK-NEXT: [[R2:%.*]] = insertelement <2 x half> [[TMP10]], half [[TMP19]], i64 1408; CHECK-NEXT: store <2 x half> [[R2]], ptr addrspace(1) [[OUT]], align 8409; CHECK-NEXT: ret void410; CHECK: [[FREM_COMPUTE]]:411; CHECK-NEXT: [[TMP20:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX16]])412; CHECK-NEXT: [[TMP21:%.*]] = extractvalue { float, i32 } [[TMP20]], 0413; CHECK-NEXT: [[TMP22:%.*]] = extractvalue { float, i32 } [[TMP20]], 1414; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP22]], 1415; CHECK-NEXT: [[AX3:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP21]], i32 11)416; CHECK-NEXT: [[TMP23:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY17]])417; CHECK-NEXT: [[TMP24:%.*]] = extractvalue { float, i32 } [[TMP23]], 0418; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { float, i32 } [[TMP23]], 1419; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP25]], 1420; CHECK-NEXT: [[AY4:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP24]], i32 1)421; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]422; CHECK-NEXT: [[AYINV:%.*]] = fdiv float 1.000000e+00, [[AY4]]423; CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i32 [[NB]], 11424; CHECK-NEXT: br i1 [[TMP26]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]425; CHECK: [[FREM_ELSE]]:426; CHECK-NEXT: [[TMP28:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP11]])427; CHECK-NEXT: [[TMP29:%.*]] = fcmp oeq float [[AX16]], [[AY17]]428; CHECK-NEXT: [[TMP38]] = select i1 [[TMP29]], half [[TMP28]], half [[TMP11]]429; CHECK-NEXT: br label %[[BB14]]430; CHECK: [[FREM_LOOP_BODY]]:431; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]432; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi float [ [[AX3]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]433; CHECK-NEXT: [[TMP30:%.*]] = fmul float [[AX_LOOP_PHI]], [[AYINV]]434; CHECK-NEXT: [[Q:%.*]] = call float @llvm.rint.f32(float [[TMP30]])435; CHECK-NEXT: [[TMP31:%.*]] = fneg float [[Q]]436; CHECK-NEXT: [[AX5:%.*]] = call float @llvm.fma.f32(float [[TMP31]], float [[AY4]], float [[AX_LOOP_PHI]])437; CHECK-NEXT: [[CLT:%.*]] = fcmp olt float [[AX5]], 0.000000e+00438; CHECK-NEXT: [[AXP:%.*]] = fadd float [[AX5]], [[AY4]]439; CHECK-NEXT: [[AX6:%.*]] = select i1 [[CLT]], float [[AXP]], float [[AX5]]440; CHECK-NEXT: [[AX_UPDATE]] = call float @llvm.ldexp.f32.i32(float [[AX6]], i32 11)441; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 11442; CHECK-NEXT: [[TMP32:%.*]] = icmp sgt i32 [[NB_IV]], 11443; CHECK-NEXT: br i1 [[TMP32]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]444; CHECK: [[FREM_LOOP_EXIT]]:445; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi float [ [[AX3]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]446; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]447; CHECK-NEXT: [[TMP33:%.*]] = sub i32 [[NB_EXIT_PHI]], 11448; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], 1449; CHECK-NEXT: [[AX7:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI]], i32 [[TMP34]])450; CHECK-NEXT: [[TMP35:%.*]] = fmul float [[AX7]], [[AYINV]]451; CHECK-NEXT: [[Q8:%.*]] = call float @llvm.rint.f32(float [[TMP35]])452; CHECK-NEXT: [[TMP36:%.*]] = fneg float [[Q8]]453; CHECK-NEXT: [[AX9:%.*]] = call float @llvm.fma.f32(float [[TMP36]], float [[AY4]], float [[AX7]])454; CHECK-NEXT: [[CLT10:%.*]] = fcmp olt float [[AX9]], 0.000000e+00455; CHECK-NEXT: [[AXP11:%.*]] = fadd float [[AX9]], [[AY4]]456; CHECK-NEXT: [[AX12:%.*]] = select i1 [[CLT10]], float [[AXP11]], float [[AX9]]457; CHECK-NEXT: [[AX13:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX12]], i32 [[EY]])458; CHECK-NEXT: [[TMP37:%.*]] = fptrunc float [[AX13]] to half459; CHECK-NEXT: [[TMP46]] = call half @llvm.copysign.f16(half [[TMP37]], half [[TMP11]])460; CHECK-NEXT: br label %[[BB14]]461; CHECK: [[FREM_COMPUTE19]]:462; CHECK-NEXT: [[TMP39:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX1]])463; CHECK-NEXT: [[TMP40:%.*]] = extractvalue { float, i32 } [[TMP39]], 0464; CHECK-NEXT: [[TMP41:%.*]] = extractvalue { float, i32 } [[TMP39]], 1465; CHECK-NEXT: [[EX21:%.*]] = sub i32 [[TMP41]], 1466; CHECK-NEXT: [[AX22:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP40]], i32 11)467; CHECK-NEXT: [[TMP42:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY2]])468; CHECK-NEXT: [[TMP43:%.*]] = extractvalue { float, i32 } [[TMP42]], 0469; CHECK-NEXT: [[TMP44:%.*]] = extractvalue { float, i32 } [[TMP42]], 1470; CHECK-NEXT: [[EY23:%.*]] = sub i32 [[TMP44]], 1471; CHECK-NEXT: [[AY24:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP43]], i32 1)472; CHECK-NEXT: [[NB25:%.*]] = sub i32 [[EX21]], [[EY23]]473; CHECK-NEXT: [[AYINV26:%.*]] = fdiv float 1.000000e+00, [[AY24]]474; CHECK-NEXT: [[TMP45:%.*]] = icmp sgt i32 [[NB25]], 11475; CHECK-NEXT: br i1 [[TMP45]], label %[[FREM_LOOP_BODY27:.*]], label %[[FREM_LOOP_EXIT28]]476; CHECK: [[FREM_ELSE20]]:477; CHECK-NEXT: [[TMP47:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP1]])478; CHECK-NEXT: [[TMP48:%.*]] = fcmp oeq float [[AX1]], [[AY2]]479; CHECK-NEXT: [[TMP57]] = select i1 [[TMP48]], half [[TMP47]], half [[TMP1]]480; CHECK-NEXT: br label %[[BB4]]481; CHECK: [[FREM_LOOP_BODY27]]:482; CHECK-NEXT: [[NB_IV29:%.*]] = phi i32 [ [[NB25]], %[[FREM_COMPUTE19]] ], [ [[NB_UPDATE37:%.*]], %[[FREM_LOOP_BODY27]] ]483; CHECK-NEXT: [[AX_LOOP_PHI30:%.*]] = phi float [ [[AX22]], %[[FREM_COMPUTE19]] ], [ [[AX_UPDATE36:%.*]], %[[FREM_LOOP_BODY27]] ]484; CHECK-NEXT: [[TMP49:%.*]] = fmul float [[AX_LOOP_PHI30]], [[AYINV26]]485; CHECK-NEXT: [[Q31:%.*]] = call float @llvm.rint.f32(float [[TMP49]])486; CHECK-NEXT: [[TMP50:%.*]] = fneg float [[Q31]]487; CHECK-NEXT: [[AX32:%.*]] = call float @llvm.fma.f32(float [[TMP50]], float [[AY24]], float [[AX_LOOP_PHI30]])488; CHECK-NEXT: [[CLT33:%.*]] = fcmp olt float [[AX32]], 0.000000e+00489; CHECK-NEXT: [[AXP34:%.*]] = fadd float [[AX32]], [[AY24]]490; CHECK-NEXT: [[AX35:%.*]] = select i1 [[CLT33]], float [[AXP34]], float [[AX32]]491; CHECK-NEXT: [[AX_UPDATE36]] = call float @llvm.ldexp.f32.i32(float [[AX35]], i32 11)492; CHECK-NEXT: [[NB_UPDATE37]] = sub i32 [[NB_IV29]], 11493; CHECK-NEXT: [[TMP51:%.*]] = icmp sgt i32 [[NB_IV29]], 11494; CHECK-NEXT: br i1 [[TMP51]], label %[[FREM_LOOP_BODY27]], label %[[FREM_LOOP_EXIT28]]495; CHECK: [[FREM_LOOP_EXIT28]]:496; CHECK-NEXT: [[AX_EXIT_PHI38:%.*]] = phi float [ [[AX22]], %[[FREM_COMPUTE19]] ], [ [[AX_LOOP_PHI30]], %[[FREM_LOOP_BODY27]] ]497; CHECK-NEXT: [[NB_EXIT_PHI39:%.*]] = phi i32 [ [[NB_IV29]], %[[FREM_LOOP_BODY27]] ], [ [[NB25]], %[[FREM_COMPUTE19]] ]498; CHECK-NEXT: [[TMP52:%.*]] = sub i32 [[NB_EXIT_PHI39]], 11499; CHECK-NEXT: [[TMP53:%.*]] = add i32 [[TMP52]], 1500; CHECK-NEXT: [[AX40:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI38]], i32 [[TMP53]])501; CHECK-NEXT: [[TMP54:%.*]] = fmul float [[AX40]], [[AYINV26]]502; CHECK-NEXT: [[Q41:%.*]] = call float @llvm.rint.f32(float [[TMP54]])503; CHECK-NEXT: [[TMP55:%.*]] = fneg float [[Q41]]504; CHECK-NEXT: [[AX42:%.*]] = call float @llvm.fma.f32(float [[TMP55]], float [[AY24]], float [[AX40]])505; CHECK-NEXT: [[CLT43:%.*]] = fcmp olt float [[AX42]], 0.000000e+00506; CHECK-NEXT: [[AXP44:%.*]] = fadd float [[AX42]], [[AY24]]507; CHECK-NEXT: [[AX45:%.*]] = select i1 [[CLT43]], float [[AXP44]], float [[AX42]]508; CHECK-NEXT: [[AX46:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX45]], i32 [[EY23]])509; CHECK-NEXT: [[TMP56:%.*]] = fptrunc float [[AX46]] to half510; CHECK-NEXT: [[TMP58]] = call half @llvm.copysign.f16(half [[TMP56]], half [[TMP1]])511; CHECK-NEXT: br label %[[BB4]]512;513 ptr addrspace(1) %in2) {514 %gep2 = getelementptr <2 x half>, ptr addrspace(1) %in2, i32 4515 %r0 = load <2 x half>, ptr addrspace(1) %in1, align 8516 %r1 = load <2 x half>, ptr addrspace(1) %gep2, align 8517 %r2 = frem <2 x half> %r0, %r1518 store <2 x half> %r2, ptr addrspace(1) %out, align 8519 ret void520}521 522define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,523; CHECK-LABEL: define amdgpu_kernel void @frem_v4f16(524; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {525; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <4 x half>, ptr addrspace(1) [[IN2]], i32 4526; CHECK-NEXT: [[R0:%.*]] = load <4 x half>, ptr addrspace(1) [[IN1]], align 16527; CHECK-NEXT: [[R1:%.*]] = load <4 x half>, ptr addrspace(1) [[GEP2]], align 16528; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x half> [[R0]], i64 0529; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x half> [[R1]], i64 0530; CHECK-NEXT: [[AX:%.*]] = call half @llvm.fabs.f16(half [[TMP1]])531; CHECK-NEXT: [[AY:%.*]] = call half @llvm.fabs.f16(half [[TMP2]])532; CHECK-NEXT: [[AX1:%.*]] = fpext half [[AX]] to float533; CHECK-NEXT: [[AY2:%.*]] = fpext half [[AY]] to float534; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt float [[AX1]], [[AY2]]535; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE85:.*]], label %[[FREM_ELSE86:.*]]536; CHECK: [[BB4:.*]]:537; CHECK-NEXT: [[RET:%.*]] = phi half [ [[TMP116:%.*]], %[[FREM_LOOP_EXIT94:.*]] ], [ [[TMP115:%.*]], %[[FREM_ELSE86]] ]538; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq half [[TMP2]], 0xH0000539; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], half 0xH7E00, half [[RET]]540; CHECK-NEXT: [[TMP7:%.*]] = call half @llvm.fabs.f16(half [[TMP1]])541; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult half [[TMP7]], 0xH7C00542; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], half [[TMP6]], half 0xH7E00543; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x half> poison, half [[TMP9]], i64 0544; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x half> [[R0]], i64 1545; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x half> [[R1]], i64 1546; CHECK-NEXT: [[AX14:%.*]] = call half @llvm.fabs.f16(half [[TMP11]])547; CHECK-NEXT: [[AY15:%.*]] = call half @llvm.fabs.f16(half [[TMP12]])548; CHECK-NEXT: [[AX16:%.*]] = fpext half [[AX14]] to float549; CHECK-NEXT: [[AY17:%.*]] = fpext half [[AY15]] to float550; CHECK-NEXT: [[TMP13:%.*]] = fcmp ogt float [[AX16]], [[AY17]]551; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE52:.*]], label %[[FREM_ELSE53:.*]]552; CHECK: [[BB14:.*]]:553; CHECK-NEXT: [[RET18:%.*]] = phi half [ [[TMP104:%.*]], %[[FREM_LOOP_EXIT61:.*]] ], [ [[TMP96:%.*]], %[[FREM_ELSE53]] ]554; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq half [[TMP12]], 0xH0000555; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], half 0xH7E00, half [[RET18]]556; CHECK-NEXT: [[TMP17:%.*]] = call half @llvm.fabs.f16(half [[TMP11]])557; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult half [[TMP17]], 0xH7C00558; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], half [[TMP16]], half 0xH7E00559; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x half> [[TMP10]], half [[TMP19]], i64 1560; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x half> [[R0]], i64 2561; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x half> [[R1]], i64 2562; CHECK-NEXT: [[AX47:%.*]] = call half @llvm.fabs.f16(half [[TMP21]])563; CHECK-NEXT: [[AY48:%.*]] = call half @llvm.fabs.f16(half [[TMP22]])564; CHECK-NEXT: [[AX49:%.*]] = fpext half [[AX47]] to float565; CHECK-NEXT: [[AY50:%.*]] = fpext half [[AY48]] to float566; CHECK-NEXT: [[TMP23:%.*]] = fcmp ogt float [[AX49]], [[AY50]]567; CHECK-NEXT: br i1 [[TMP23]], label %[[FREM_COMPUTE19:.*]], label %[[FREM_ELSE20:.*]]568; CHECK: [[BB24:.*]]:569; CHECK-NEXT: [[RET51:%.*]] = phi half [ [[TMP85:%.*]], %[[FREM_LOOP_EXIT28:.*]] ], [ [[TMP77:%.*]], %[[FREM_ELSE20]] ]570; CHECK-NEXT: [[TMP25:%.*]] = fcmp ueq half [[TMP22]], 0xH0000571; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], half 0xH7E00, half [[RET51]]572; CHECK-NEXT: [[TMP27:%.*]] = call half @llvm.fabs.f16(half [[TMP21]])573; CHECK-NEXT: [[TMP28:%.*]] = fcmp ult half [[TMP27]], 0xH7C00574; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], half [[TMP26]], half 0xH7E00575; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x half> [[TMP20]], half [[TMP29]], i64 2576; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x half> [[R0]], i64 3577; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x half> [[R1]], i64 3578; CHECK-NEXT: [[AX80:%.*]] = call half @llvm.fabs.f16(half [[TMP31]])579; CHECK-NEXT: [[AY81:%.*]] = call half @llvm.fabs.f16(half [[TMP32]])580; CHECK-NEXT: [[AX82:%.*]] = fpext half [[AX80]] to float581; CHECK-NEXT: [[AY83:%.*]] = fpext half [[AY81]] to float582; CHECK-NEXT: [[TMP33:%.*]] = fcmp ogt float [[AX82]], [[AY83]]583; CHECK-NEXT: br i1 [[TMP33]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]584; CHECK: [[BB34:.*]]:585; CHECK-NEXT: [[RET84:%.*]] = phi half [ [[TMP66:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP58:%.*]], %[[FREM_ELSE]] ]586; CHECK-NEXT: [[TMP35:%.*]] = fcmp ueq half [[TMP32]], 0xH0000587; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], half 0xH7E00, half [[RET84]]588; CHECK-NEXT: [[TMP37:%.*]] = call half @llvm.fabs.f16(half [[TMP31]])589; CHECK-NEXT: [[TMP38:%.*]] = fcmp ult half [[TMP37]], 0xH7C00590; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], half [[TMP36]], half 0xH7E00591; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x half> [[TMP30]], half [[TMP39]], i64 3592; CHECK-NEXT: store <4 x half> [[R2]], ptr addrspace(1) [[OUT]], align 16593; CHECK-NEXT: ret void594; CHECK: [[FREM_COMPUTE]]:595; CHECK-NEXT: [[TMP40:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX82]])596; CHECK-NEXT: [[TMP41:%.*]] = extractvalue { float, i32 } [[TMP40]], 0597; CHECK-NEXT: [[TMP42:%.*]] = extractvalue { float, i32 } [[TMP40]], 1598; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP42]], 1599; CHECK-NEXT: [[AX3:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP41]], i32 11)600; CHECK-NEXT: [[TMP43:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY83]])601; CHECK-NEXT: [[TMP44:%.*]] = extractvalue { float, i32 } [[TMP43]], 0602; CHECK-NEXT: [[TMP45:%.*]] = extractvalue { float, i32 } [[TMP43]], 1603; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP45]], 1604; CHECK-NEXT: [[AY4:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP44]], i32 1)605; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]606; CHECK-NEXT: [[AYINV:%.*]] = fdiv float 1.000000e+00, [[AY4]]607; CHECK-NEXT: [[TMP46:%.*]] = icmp sgt i32 [[NB]], 11608; CHECK-NEXT: br i1 [[TMP46]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]609; CHECK: [[FREM_ELSE]]:610; CHECK-NEXT: [[TMP48:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP31]])611; CHECK-NEXT: [[TMP49:%.*]] = fcmp oeq float [[AX82]], [[AY83]]612; CHECK-NEXT: [[TMP58]] = select i1 [[TMP49]], half [[TMP48]], half [[TMP31]]613; CHECK-NEXT: br label %[[BB34]]614; CHECK: [[FREM_LOOP_BODY]]:615; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]616; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi float [ [[AX3]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]617; CHECK-NEXT: [[TMP50:%.*]] = fmul float [[AX_LOOP_PHI]], [[AYINV]]618; CHECK-NEXT: [[Q:%.*]] = call float @llvm.rint.f32(float [[TMP50]])619; CHECK-NEXT: [[TMP51:%.*]] = fneg float [[Q]]620; CHECK-NEXT: [[AX5:%.*]] = call float @llvm.fma.f32(float [[TMP51]], float [[AY4]], float [[AX_LOOP_PHI]])621; CHECK-NEXT: [[CLT:%.*]] = fcmp olt float [[AX5]], 0.000000e+00622; CHECK-NEXT: [[AXP:%.*]] = fadd float [[AX5]], [[AY4]]623; CHECK-NEXT: [[AX6:%.*]] = select i1 [[CLT]], float [[AXP]], float [[AX5]]624; CHECK-NEXT: [[AX_UPDATE]] = call float @llvm.ldexp.f32.i32(float [[AX6]], i32 11)625; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 11626; CHECK-NEXT: [[TMP52:%.*]] = icmp sgt i32 [[NB_IV]], 11627; CHECK-NEXT: br i1 [[TMP52]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]628; CHECK: [[FREM_LOOP_EXIT]]:629; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi float [ [[AX3]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]630; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]631; CHECK-NEXT: [[TMP53:%.*]] = sub i32 [[NB_EXIT_PHI]], 11632; CHECK-NEXT: [[TMP54:%.*]] = add i32 [[TMP53]], 1633; CHECK-NEXT: [[AX7:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI]], i32 [[TMP54]])634; CHECK-NEXT: [[TMP55:%.*]] = fmul float [[AX7]], [[AYINV]]635; CHECK-NEXT: [[Q8:%.*]] = call float @llvm.rint.f32(float [[TMP55]])636; CHECK-NEXT: [[TMP56:%.*]] = fneg float [[Q8]]637; CHECK-NEXT: [[AX9:%.*]] = call float @llvm.fma.f32(float [[TMP56]], float [[AY4]], float [[AX7]])638; CHECK-NEXT: [[CLT10:%.*]] = fcmp olt float [[AX9]], 0.000000e+00639; CHECK-NEXT: [[AXP11:%.*]] = fadd float [[AX9]], [[AY4]]640; CHECK-NEXT: [[AX12:%.*]] = select i1 [[CLT10]], float [[AXP11]], float [[AX9]]641; CHECK-NEXT: [[AX13:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX12]], i32 [[EY]])642; CHECK-NEXT: [[TMP57:%.*]] = fptrunc float [[AX13]] to half643; CHECK-NEXT: [[TMP66]] = call half @llvm.copysign.f16(half [[TMP57]], half [[TMP31]])644; CHECK-NEXT: br label %[[BB34]]645; CHECK: [[FREM_COMPUTE19]]:646; CHECK-NEXT: [[TMP59:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX49]])647; CHECK-NEXT: [[TMP60:%.*]] = extractvalue { float, i32 } [[TMP59]], 0648; CHECK-NEXT: [[TMP61:%.*]] = extractvalue { float, i32 } [[TMP59]], 1649; CHECK-NEXT: [[EX21:%.*]] = sub i32 [[TMP61]], 1650; CHECK-NEXT: [[AX22:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP60]], i32 11)651; CHECK-NEXT: [[TMP62:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY50]])652; CHECK-NEXT: [[TMP63:%.*]] = extractvalue { float, i32 } [[TMP62]], 0653; CHECK-NEXT: [[TMP64:%.*]] = extractvalue { float, i32 } [[TMP62]], 1654; CHECK-NEXT: [[EY23:%.*]] = sub i32 [[TMP64]], 1655; CHECK-NEXT: [[AY24:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP63]], i32 1)656; CHECK-NEXT: [[NB25:%.*]] = sub i32 [[EX21]], [[EY23]]657; CHECK-NEXT: [[AYINV26:%.*]] = fdiv float 1.000000e+00, [[AY24]]658; CHECK-NEXT: [[TMP65:%.*]] = icmp sgt i32 [[NB25]], 11659; CHECK-NEXT: br i1 [[TMP65]], label %[[FREM_LOOP_BODY27:.*]], label %[[FREM_LOOP_EXIT28]]660; CHECK: [[FREM_ELSE20]]:661; CHECK-NEXT: [[TMP67:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP21]])662; CHECK-NEXT: [[TMP68:%.*]] = fcmp oeq float [[AX49]], [[AY50]]663; CHECK-NEXT: [[TMP77]] = select i1 [[TMP68]], half [[TMP67]], half [[TMP21]]664; CHECK-NEXT: br label %[[BB24]]665; CHECK: [[FREM_LOOP_BODY27]]:666; CHECK-NEXT: [[NB_IV29:%.*]] = phi i32 [ [[NB25]], %[[FREM_COMPUTE19]] ], [ [[NB_UPDATE37:%.*]], %[[FREM_LOOP_BODY27]] ]667; CHECK-NEXT: [[AX_LOOP_PHI30:%.*]] = phi float [ [[AX22]], %[[FREM_COMPUTE19]] ], [ [[AX_UPDATE36:%.*]], %[[FREM_LOOP_BODY27]] ]668; CHECK-NEXT: [[TMP69:%.*]] = fmul float [[AX_LOOP_PHI30]], [[AYINV26]]669; CHECK-NEXT: [[Q31:%.*]] = call float @llvm.rint.f32(float [[TMP69]])670; CHECK-NEXT: [[TMP70:%.*]] = fneg float [[Q31]]671; CHECK-NEXT: [[AX32:%.*]] = call float @llvm.fma.f32(float [[TMP70]], float [[AY24]], float [[AX_LOOP_PHI30]])672; CHECK-NEXT: [[CLT33:%.*]] = fcmp olt float [[AX32]], 0.000000e+00673; CHECK-NEXT: [[AXP34:%.*]] = fadd float [[AX32]], [[AY24]]674; CHECK-NEXT: [[AX35:%.*]] = select i1 [[CLT33]], float [[AXP34]], float [[AX32]]675; CHECK-NEXT: [[AX_UPDATE36]] = call float @llvm.ldexp.f32.i32(float [[AX35]], i32 11)676; CHECK-NEXT: [[NB_UPDATE37]] = sub i32 [[NB_IV29]], 11677; CHECK-NEXT: [[TMP71:%.*]] = icmp sgt i32 [[NB_IV29]], 11678; CHECK-NEXT: br i1 [[TMP71]], label %[[FREM_LOOP_BODY27]], label %[[FREM_LOOP_EXIT28]]679; CHECK: [[FREM_LOOP_EXIT28]]:680; CHECK-NEXT: [[AX_EXIT_PHI38:%.*]] = phi float [ [[AX22]], %[[FREM_COMPUTE19]] ], [ [[AX_LOOP_PHI30]], %[[FREM_LOOP_BODY27]] ]681; CHECK-NEXT: [[NB_EXIT_PHI39:%.*]] = phi i32 [ [[NB_IV29]], %[[FREM_LOOP_BODY27]] ], [ [[NB25]], %[[FREM_COMPUTE19]] ]682; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[NB_EXIT_PHI39]], 11683; CHECK-NEXT: [[TMP73:%.*]] = add i32 [[TMP72]], 1684; CHECK-NEXT: [[AX40:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI38]], i32 [[TMP73]])685; CHECK-NEXT: [[TMP74:%.*]] = fmul float [[AX40]], [[AYINV26]]686; CHECK-NEXT: [[Q41:%.*]] = call float @llvm.rint.f32(float [[TMP74]])687; CHECK-NEXT: [[TMP75:%.*]] = fneg float [[Q41]]688; CHECK-NEXT: [[AX42:%.*]] = call float @llvm.fma.f32(float [[TMP75]], float [[AY24]], float [[AX40]])689; CHECK-NEXT: [[CLT43:%.*]] = fcmp olt float [[AX42]], 0.000000e+00690; CHECK-NEXT: [[AXP44:%.*]] = fadd float [[AX42]], [[AY24]]691; CHECK-NEXT: [[AX45:%.*]] = select i1 [[CLT43]], float [[AXP44]], float [[AX42]]692; CHECK-NEXT: [[AX46:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX45]], i32 [[EY23]])693; CHECK-NEXT: [[TMP76:%.*]] = fptrunc float [[AX46]] to half694; CHECK-NEXT: [[TMP85]] = call half @llvm.copysign.f16(half [[TMP76]], half [[TMP21]])695; CHECK-NEXT: br label %[[BB24]]696; CHECK: [[FREM_COMPUTE52]]:697; CHECK-NEXT: [[TMP78:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX16]])698; CHECK-NEXT: [[TMP79:%.*]] = extractvalue { float, i32 } [[TMP78]], 0699; CHECK-NEXT: [[TMP80:%.*]] = extractvalue { float, i32 } [[TMP78]], 1700; CHECK-NEXT: [[EX54:%.*]] = sub i32 [[TMP80]], 1701; CHECK-NEXT: [[AX55:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP79]], i32 11)702; CHECK-NEXT: [[TMP81:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY17]])703; CHECK-NEXT: [[TMP82:%.*]] = extractvalue { float, i32 } [[TMP81]], 0704; CHECK-NEXT: [[TMP83:%.*]] = extractvalue { float, i32 } [[TMP81]], 1705; CHECK-NEXT: [[EY56:%.*]] = sub i32 [[TMP83]], 1706; CHECK-NEXT: [[AY57:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP82]], i32 1)707; CHECK-NEXT: [[NB58:%.*]] = sub i32 [[EX54]], [[EY56]]708; CHECK-NEXT: [[AYINV59:%.*]] = fdiv float 1.000000e+00, [[AY57]]709; CHECK-NEXT: [[TMP84:%.*]] = icmp sgt i32 [[NB58]], 11710; CHECK-NEXT: br i1 [[TMP84]], label %[[FREM_LOOP_BODY60:.*]], label %[[FREM_LOOP_EXIT61]]711; CHECK: [[FREM_ELSE53]]:712; CHECK-NEXT: [[TMP86:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP11]])713; CHECK-NEXT: [[TMP87:%.*]] = fcmp oeq float [[AX16]], [[AY17]]714; CHECK-NEXT: [[TMP96]] = select i1 [[TMP87]], half [[TMP86]], half [[TMP11]]715; CHECK-NEXT: br label %[[BB14]]716; CHECK: [[FREM_LOOP_BODY60]]:717; CHECK-NEXT: [[NB_IV62:%.*]] = phi i32 [ [[NB58]], %[[FREM_COMPUTE52]] ], [ [[NB_UPDATE70:%.*]], %[[FREM_LOOP_BODY60]] ]718; CHECK-NEXT: [[AX_LOOP_PHI63:%.*]] = phi float [ [[AX55]], %[[FREM_COMPUTE52]] ], [ [[AX_UPDATE69:%.*]], %[[FREM_LOOP_BODY60]] ]719; CHECK-NEXT: [[TMP88:%.*]] = fmul float [[AX_LOOP_PHI63]], [[AYINV59]]720; CHECK-NEXT: [[Q64:%.*]] = call float @llvm.rint.f32(float [[TMP88]])721; CHECK-NEXT: [[TMP89:%.*]] = fneg float [[Q64]]722; CHECK-NEXT: [[AX65:%.*]] = call float @llvm.fma.f32(float [[TMP89]], float [[AY57]], float [[AX_LOOP_PHI63]])723; CHECK-NEXT: [[CLT66:%.*]] = fcmp olt float [[AX65]], 0.000000e+00724; CHECK-NEXT: [[AXP67:%.*]] = fadd float [[AX65]], [[AY57]]725; CHECK-NEXT: [[AX68:%.*]] = select i1 [[CLT66]], float [[AXP67]], float [[AX65]]726; CHECK-NEXT: [[AX_UPDATE69]] = call float @llvm.ldexp.f32.i32(float [[AX68]], i32 11)727; CHECK-NEXT: [[NB_UPDATE70]] = sub i32 [[NB_IV62]], 11728; CHECK-NEXT: [[TMP90:%.*]] = icmp sgt i32 [[NB_IV62]], 11729; CHECK-NEXT: br i1 [[TMP90]], label %[[FREM_LOOP_BODY60]], label %[[FREM_LOOP_EXIT61]]730; CHECK: [[FREM_LOOP_EXIT61]]:731; CHECK-NEXT: [[AX_EXIT_PHI71:%.*]] = phi float [ [[AX55]], %[[FREM_COMPUTE52]] ], [ [[AX_LOOP_PHI63]], %[[FREM_LOOP_BODY60]] ]732; CHECK-NEXT: [[NB_EXIT_PHI72:%.*]] = phi i32 [ [[NB_IV62]], %[[FREM_LOOP_BODY60]] ], [ [[NB58]], %[[FREM_COMPUTE52]] ]733; CHECK-NEXT: [[TMP91:%.*]] = sub i32 [[NB_EXIT_PHI72]], 11734; CHECK-NEXT: [[TMP92:%.*]] = add i32 [[TMP91]], 1735; CHECK-NEXT: [[AX73:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI71]], i32 [[TMP92]])736; CHECK-NEXT: [[TMP93:%.*]] = fmul float [[AX73]], [[AYINV59]]737; CHECK-NEXT: [[Q74:%.*]] = call float @llvm.rint.f32(float [[TMP93]])738; CHECK-NEXT: [[TMP94:%.*]] = fneg float [[Q74]]739; CHECK-NEXT: [[AX75:%.*]] = call float @llvm.fma.f32(float [[TMP94]], float [[AY57]], float [[AX73]])740; CHECK-NEXT: [[CLT76:%.*]] = fcmp olt float [[AX75]], 0.000000e+00741; CHECK-NEXT: [[AXP77:%.*]] = fadd float [[AX75]], [[AY57]]742; CHECK-NEXT: [[AX78:%.*]] = select i1 [[CLT76]], float [[AXP77]], float [[AX75]]743; CHECK-NEXT: [[AX79:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX78]], i32 [[EY56]])744; CHECK-NEXT: [[TMP95:%.*]] = fptrunc float [[AX79]] to half745; CHECK-NEXT: [[TMP104]] = call half @llvm.copysign.f16(half [[TMP95]], half [[TMP11]])746; CHECK-NEXT: br label %[[BB14]]747; CHECK: [[FREM_COMPUTE85]]:748; CHECK-NEXT: [[TMP97:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX1]])749; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { float, i32 } [[TMP97]], 0750; CHECK-NEXT: [[TMP99:%.*]] = extractvalue { float, i32 } [[TMP97]], 1751; CHECK-NEXT: [[EX87:%.*]] = sub i32 [[TMP99]], 1752; CHECK-NEXT: [[AX88:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP98]], i32 11)753; CHECK-NEXT: [[TMP100:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY2]])754; CHECK-NEXT: [[TMP101:%.*]] = extractvalue { float, i32 } [[TMP100]], 0755; CHECK-NEXT: [[TMP102:%.*]] = extractvalue { float, i32 } [[TMP100]], 1756; CHECK-NEXT: [[EY89:%.*]] = sub i32 [[TMP102]], 1757; CHECK-NEXT: [[AY90:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP101]], i32 1)758; CHECK-NEXT: [[NB91:%.*]] = sub i32 [[EX87]], [[EY89]]759; CHECK-NEXT: [[AYINV92:%.*]] = fdiv float 1.000000e+00, [[AY90]]760; CHECK-NEXT: [[TMP103:%.*]] = icmp sgt i32 [[NB91]], 11761; CHECK-NEXT: br i1 [[TMP103]], label %[[FREM_LOOP_BODY93:.*]], label %[[FREM_LOOP_EXIT94]]762; CHECK: [[FREM_ELSE86]]:763; CHECK-NEXT: [[TMP105:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP1]])764; CHECK-NEXT: [[TMP106:%.*]] = fcmp oeq float [[AX1]], [[AY2]]765; CHECK-NEXT: [[TMP115]] = select i1 [[TMP106]], half [[TMP105]], half [[TMP1]]766; CHECK-NEXT: br label %[[BB4]]767; CHECK: [[FREM_LOOP_BODY93]]:768; CHECK-NEXT: [[NB_IV95:%.*]] = phi i32 [ [[NB91]], %[[FREM_COMPUTE85]] ], [ [[NB_UPDATE103:%.*]], %[[FREM_LOOP_BODY93]] ]769; CHECK-NEXT: [[AX_LOOP_PHI96:%.*]] = phi float [ [[AX88]], %[[FREM_COMPUTE85]] ], [ [[AX_UPDATE102:%.*]], %[[FREM_LOOP_BODY93]] ]770; CHECK-NEXT: [[TMP107:%.*]] = fmul float [[AX_LOOP_PHI96]], [[AYINV92]]771; CHECK-NEXT: [[Q97:%.*]] = call float @llvm.rint.f32(float [[TMP107]])772; CHECK-NEXT: [[TMP108:%.*]] = fneg float [[Q97]]773; CHECK-NEXT: [[AX98:%.*]] = call float @llvm.fma.f32(float [[TMP108]], float [[AY90]], float [[AX_LOOP_PHI96]])774; CHECK-NEXT: [[CLT99:%.*]] = fcmp olt float [[AX98]], 0.000000e+00775; CHECK-NEXT: [[AXP100:%.*]] = fadd float [[AX98]], [[AY90]]776; CHECK-NEXT: [[AX101:%.*]] = select i1 [[CLT99]], float [[AXP100]], float [[AX98]]777; CHECK-NEXT: [[AX_UPDATE102]] = call float @llvm.ldexp.f32.i32(float [[AX101]], i32 11)778; CHECK-NEXT: [[NB_UPDATE103]] = sub i32 [[NB_IV95]], 11779; CHECK-NEXT: [[TMP109:%.*]] = icmp sgt i32 [[NB_IV95]], 11780; CHECK-NEXT: br i1 [[TMP109]], label %[[FREM_LOOP_BODY93]], label %[[FREM_LOOP_EXIT94]]781; CHECK: [[FREM_LOOP_EXIT94]]:782; CHECK-NEXT: [[AX_EXIT_PHI104:%.*]] = phi float [ [[AX88]], %[[FREM_COMPUTE85]] ], [ [[AX_LOOP_PHI96]], %[[FREM_LOOP_BODY93]] ]783; CHECK-NEXT: [[NB_EXIT_PHI105:%.*]] = phi i32 [ [[NB_IV95]], %[[FREM_LOOP_BODY93]] ], [ [[NB91]], %[[FREM_COMPUTE85]] ]784; CHECK-NEXT: [[TMP110:%.*]] = sub i32 [[NB_EXIT_PHI105]], 11785; CHECK-NEXT: [[TMP111:%.*]] = add i32 [[TMP110]], 1786; CHECK-NEXT: [[AX106:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI104]], i32 [[TMP111]])787; CHECK-NEXT: [[TMP112:%.*]] = fmul float [[AX106]], [[AYINV92]]788; CHECK-NEXT: [[Q107:%.*]] = call float @llvm.rint.f32(float [[TMP112]])789; CHECK-NEXT: [[TMP113:%.*]] = fneg float [[Q107]]790; CHECK-NEXT: [[AX108:%.*]] = call float @llvm.fma.f32(float [[TMP113]], float [[AY90]], float [[AX106]])791; CHECK-NEXT: [[CLT109:%.*]] = fcmp olt float [[AX108]], 0.000000e+00792; CHECK-NEXT: [[AXP110:%.*]] = fadd float [[AX108]], [[AY90]]793; CHECK-NEXT: [[AX111:%.*]] = select i1 [[CLT109]], float [[AXP110]], float [[AX108]]794; CHECK-NEXT: [[AX112:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX111]], i32 [[EY89]])795; CHECK-NEXT: [[TMP114:%.*]] = fptrunc float [[AX112]] to half796; CHECK-NEXT: [[TMP116]] = call half @llvm.copysign.f16(half [[TMP114]], half [[TMP1]])797; CHECK-NEXT: br label %[[BB4]]798;799 ptr addrspace(1) %in2) {800 %gep2 = getelementptr <4 x half>, ptr addrspace(1) %in2, i32 4801 %r0 = load <4 x half>, ptr addrspace(1) %in1, align 16802 %r1 = load <4 x half>, ptr addrspace(1) %gep2, align 16803 %r2 = frem <4 x half> %r0, %r1804 store <4 x half> %r2, ptr addrspace(1) %out, align 16805 ret void806}807 808define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,809; CHECK-LABEL: define amdgpu_kernel void @frem_v2f32(810; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {811; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <2 x float>, ptr addrspace(1) [[IN2]], i32 4812; CHECK-NEXT: [[R0:%.*]] = load <2 x float>, ptr addrspace(1) [[IN1]], align 8813; CHECK-NEXT: [[R1:%.*]] = load <2 x float>, ptr addrspace(1) [[GEP2]], align 8814; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[R0]], i64 0815; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[R1]], i64 0816; CHECK-NEXT: [[AX:%.*]] = call float @llvm.fabs.f32(float [[TMP1]])817; CHECK-NEXT: [[AY:%.*]] = call float @llvm.fabs.f32(float [[TMP2]])818; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt float [[AX]], [[AY]]819; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE15:.*]], label %[[FREM_ELSE16:.*]]820; CHECK: [[BB4:.*]]:821; CHECK-NEXT: [[RET:%.*]] = phi float [ [[TMP56:%.*]], %[[FREM_LOOP_EXIT24:.*]] ], [ [[TMP55:%.*]], %[[FREM_ELSE16]] ]822; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq float [[TMP2]], 0.000000e+00823; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float 0x7FF8000000000000, float [[RET]]824; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.fabs.f32(float [[TMP1]])825; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult float [[TMP7]], 0x7FF0000000000000826; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float 0x7FF8000000000000827; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x float> poison, float [[TMP9]], i64 0828; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x float> [[R0]], i64 1829; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x float> [[R1]], i64 1830; CHECK-NEXT: [[AX12:%.*]] = call float @llvm.fabs.f32(float [[TMP11]])831; CHECK-NEXT: [[AY13:%.*]] = call float @llvm.fabs.f32(float [[TMP12]])832; CHECK-NEXT: [[TMP13:%.*]] = fcmp ogt float [[AX12]], [[AY13]]833; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]834; CHECK: [[BB14:.*]]:835; CHECK-NEXT: [[RET14:%.*]] = phi float [ [[TMP45:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP37:%.*]], %[[FREM_ELSE]] ]836; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq float [[TMP12]], 0.000000e+00837; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], float 0x7FF8000000000000, float [[RET14]]838; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.fabs.f32(float [[TMP11]])839; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult float [[TMP17]], 0x7FF0000000000000840; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float 0x7FF8000000000000841; CHECK-NEXT: [[R2:%.*]] = insertelement <2 x float> [[TMP10]], float [[TMP19]], i64 1842; CHECK-NEXT: store <2 x float> [[R2]], ptr addrspace(1) [[OUT]], align 8843; CHECK-NEXT: ret void844; CHECK: [[FREM_COMPUTE]]:845; CHECK-NEXT: [[TMP20:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX12]])846; CHECK-NEXT: [[TMP21:%.*]] = extractvalue { float, i32 } [[TMP20]], 0847; CHECK-NEXT: [[TMP22:%.*]] = extractvalue { float, i32 } [[TMP20]], 1848; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP22]], 1849; CHECK-NEXT: [[AX1:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP21]], i32 12)850; CHECK-NEXT: [[TMP23:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY13]])851; CHECK-NEXT: [[TMP24:%.*]] = extractvalue { float, i32 } [[TMP23]], 0852; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { float, i32 } [[TMP23]], 1853; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP25]], 1854; CHECK-NEXT: [[AY2:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP24]], i32 1)855; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]856; CHECK-NEXT: [[AYINV:%.*]] = fdiv float 1.000000e+00, [[AY2]]857; CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i32 [[NB]], 12858; CHECK-NEXT: br i1 [[TMP26]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]859; CHECK: [[FREM_ELSE]]:860; CHECK-NEXT: [[TMP28:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP11]])861; CHECK-NEXT: [[TMP29:%.*]] = fcmp oeq float [[AX12]], [[AY13]]862; CHECK-NEXT: [[TMP37]] = select i1 [[TMP29]], float [[TMP28]], float [[TMP11]]863; CHECK-NEXT: br label %[[BB14]]864; CHECK: [[FREM_LOOP_BODY]]:865; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]866; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi float [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]867; CHECK-NEXT: [[TMP30:%.*]] = fmul float [[AX_LOOP_PHI]], [[AYINV]]868; CHECK-NEXT: [[Q:%.*]] = call float @llvm.rint.f32(float [[TMP30]])869; CHECK-NEXT: [[TMP31:%.*]] = fneg float [[Q]]870; CHECK-NEXT: [[AX3:%.*]] = call float @llvm.fma.f32(float [[TMP31]], float [[AY2]], float [[AX_LOOP_PHI]])871; CHECK-NEXT: [[CLT:%.*]] = fcmp olt float [[AX3]], 0.000000e+00872; CHECK-NEXT: [[AXP:%.*]] = fadd float [[AX3]], [[AY2]]873; CHECK-NEXT: [[AX4:%.*]] = select i1 [[CLT]], float [[AXP]], float [[AX3]]874; CHECK-NEXT: [[AX_UPDATE]] = call float @llvm.ldexp.f32.i32(float [[AX4]], i32 12)875; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 12876; CHECK-NEXT: [[TMP32:%.*]] = icmp sgt i32 [[NB_IV]], 12877; CHECK-NEXT: br i1 [[TMP32]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]878; CHECK: [[FREM_LOOP_EXIT]]:879; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi float [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]880; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]881; CHECK-NEXT: [[TMP33:%.*]] = sub i32 [[NB_EXIT_PHI]], 12882; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], 1883; CHECK-NEXT: [[AX5:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI]], i32 [[TMP34]])884; CHECK-NEXT: [[TMP35:%.*]] = fmul float [[AX5]], [[AYINV]]885; CHECK-NEXT: [[Q6:%.*]] = call float @llvm.rint.f32(float [[TMP35]])886; CHECK-NEXT: [[TMP36:%.*]] = fneg float [[Q6]]887; CHECK-NEXT: [[AX7:%.*]] = call float @llvm.fma.f32(float [[TMP36]], float [[AY2]], float [[AX5]])888; CHECK-NEXT: [[CLT8:%.*]] = fcmp olt float [[AX7]], 0.000000e+00889; CHECK-NEXT: [[AXP9:%.*]] = fadd float [[AX7]], [[AY2]]890; CHECK-NEXT: [[AX10:%.*]] = select i1 [[CLT8]], float [[AXP9]], float [[AX7]]891; CHECK-NEXT: [[AX11:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX10]], i32 [[EY]])892; CHECK-NEXT: [[TMP45]] = call float @llvm.copysign.f32(float [[AX11]], float [[TMP11]])893; CHECK-NEXT: br label %[[BB14]]894; CHECK: [[FREM_COMPUTE15]]:895; CHECK-NEXT: [[TMP38:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX]])896; CHECK-NEXT: [[TMP39:%.*]] = extractvalue { float, i32 } [[TMP38]], 0897; CHECK-NEXT: [[TMP40:%.*]] = extractvalue { float, i32 } [[TMP38]], 1898; CHECK-NEXT: [[EX17:%.*]] = sub i32 [[TMP40]], 1899; CHECK-NEXT: [[AX18:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP39]], i32 12)900; CHECK-NEXT: [[TMP41:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY]])901; CHECK-NEXT: [[TMP42:%.*]] = extractvalue { float, i32 } [[TMP41]], 0902; CHECK-NEXT: [[TMP43:%.*]] = extractvalue { float, i32 } [[TMP41]], 1903; CHECK-NEXT: [[EY19:%.*]] = sub i32 [[TMP43]], 1904; CHECK-NEXT: [[AY20:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP42]], i32 1)905; CHECK-NEXT: [[NB21:%.*]] = sub i32 [[EX17]], [[EY19]]906; CHECK-NEXT: [[AYINV22:%.*]] = fdiv float 1.000000e+00, [[AY20]]907; CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i32 [[NB21]], 12908; CHECK-NEXT: br i1 [[TMP44]], label %[[FREM_LOOP_BODY23:.*]], label %[[FREM_LOOP_EXIT24]]909; CHECK: [[FREM_ELSE16]]:910; CHECK-NEXT: [[TMP46:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP1]])911; CHECK-NEXT: [[TMP47:%.*]] = fcmp oeq float [[AX]], [[AY]]912; CHECK-NEXT: [[TMP55]] = select i1 [[TMP47]], float [[TMP46]], float [[TMP1]]913; CHECK-NEXT: br label %[[BB4]]914; CHECK: [[FREM_LOOP_BODY23]]:915; CHECK-NEXT: [[NB_IV25:%.*]] = phi i32 [ [[NB21]], %[[FREM_COMPUTE15]] ], [ [[NB_UPDATE33:%.*]], %[[FREM_LOOP_BODY23]] ]916; CHECK-NEXT: [[AX_LOOP_PHI26:%.*]] = phi float [ [[AX18]], %[[FREM_COMPUTE15]] ], [ [[AX_UPDATE32:%.*]], %[[FREM_LOOP_BODY23]] ]917; CHECK-NEXT: [[TMP48:%.*]] = fmul float [[AX_LOOP_PHI26]], [[AYINV22]]918; CHECK-NEXT: [[Q27:%.*]] = call float @llvm.rint.f32(float [[TMP48]])919; CHECK-NEXT: [[TMP49:%.*]] = fneg float [[Q27]]920; CHECK-NEXT: [[AX28:%.*]] = call float @llvm.fma.f32(float [[TMP49]], float [[AY20]], float [[AX_LOOP_PHI26]])921; CHECK-NEXT: [[CLT29:%.*]] = fcmp olt float [[AX28]], 0.000000e+00922; CHECK-NEXT: [[AXP30:%.*]] = fadd float [[AX28]], [[AY20]]923; CHECK-NEXT: [[AX31:%.*]] = select i1 [[CLT29]], float [[AXP30]], float [[AX28]]924; CHECK-NEXT: [[AX_UPDATE32]] = call float @llvm.ldexp.f32.i32(float [[AX31]], i32 12)925; CHECK-NEXT: [[NB_UPDATE33]] = sub i32 [[NB_IV25]], 12926; CHECK-NEXT: [[TMP50:%.*]] = icmp sgt i32 [[NB_IV25]], 12927; CHECK-NEXT: br i1 [[TMP50]], label %[[FREM_LOOP_BODY23]], label %[[FREM_LOOP_EXIT24]]928; CHECK: [[FREM_LOOP_EXIT24]]:929; CHECK-NEXT: [[AX_EXIT_PHI34:%.*]] = phi float [ [[AX18]], %[[FREM_COMPUTE15]] ], [ [[AX_LOOP_PHI26]], %[[FREM_LOOP_BODY23]] ]930; CHECK-NEXT: [[NB_EXIT_PHI35:%.*]] = phi i32 [ [[NB_IV25]], %[[FREM_LOOP_BODY23]] ], [ [[NB21]], %[[FREM_COMPUTE15]] ]931; CHECK-NEXT: [[TMP51:%.*]] = sub i32 [[NB_EXIT_PHI35]], 12932; CHECK-NEXT: [[TMP52:%.*]] = add i32 [[TMP51]], 1933; CHECK-NEXT: [[AX36:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI34]], i32 [[TMP52]])934; CHECK-NEXT: [[TMP53:%.*]] = fmul float [[AX36]], [[AYINV22]]935; CHECK-NEXT: [[Q37:%.*]] = call float @llvm.rint.f32(float [[TMP53]])936; CHECK-NEXT: [[TMP54:%.*]] = fneg float [[Q37]]937; CHECK-NEXT: [[AX38:%.*]] = call float @llvm.fma.f32(float [[TMP54]], float [[AY20]], float [[AX36]])938; CHECK-NEXT: [[CLT39:%.*]] = fcmp olt float [[AX38]], 0.000000e+00939; CHECK-NEXT: [[AXP40:%.*]] = fadd float [[AX38]], [[AY20]]940; CHECK-NEXT: [[AX41:%.*]] = select i1 [[CLT39]], float [[AXP40]], float [[AX38]]941; CHECK-NEXT: [[AX42:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX41]], i32 [[EY19]])942; CHECK-NEXT: [[TMP56]] = call float @llvm.copysign.f32(float [[AX42]], float [[TMP1]])943; CHECK-NEXT: br label %[[BB4]]944;945 ptr addrspace(1) %in2) {946 %gep2 = getelementptr <2 x float>, ptr addrspace(1) %in2, i32 4947 %r0 = load <2 x float>, ptr addrspace(1) %in1, align 8948 %r1 = load <2 x float>, ptr addrspace(1) %gep2, align 8949 %r2 = frem <2 x float> %r0, %r1950 store <2 x float> %r2, ptr addrspace(1) %out, align 8951 ret void952}953 954define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,955; CHECK-LABEL: define amdgpu_kernel void @frem_v4f32(956; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {957; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <4 x float>, ptr addrspace(1) [[IN2]], i32 4958; CHECK-NEXT: [[R0:%.*]] = load <4 x float>, ptr addrspace(1) [[IN1]], align 16959; CHECK-NEXT: [[R1:%.*]] = load <4 x float>, ptr addrspace(1) [[GEP2]], align 16960; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[R0]], i64 0961; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[R1]], i64 0962; CHECK-NEXT: [[AX:%.*]] = call float @llvm.fabs.f32(float [[TMP1]])963; CHECK-NEXT: [[AY:%.*]] = call float @llvm.fabs.f32(float [[TMP2]])964; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt float [[AX]], [[AY]]965; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE77:.*]], label %[[FREM_ELSE78:.*]]966; CHECK: [[BB4:.*]]:967; CHECK-NEXT: [[RET:%.*]] = phi float [ [[TMP112:%.*]], %[[FREM_LOOP_EXIT86:.*]] ], [ [[TMP111:%.*]], %[[FREM_ELSE78]] ]968; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq float [[TMP2]], 0.000000e+00969; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float 0x7FF8000000000000, float [[RET]]970; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.fabs.f32(float [[TMP1]])971; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult float [[TMP7]], 0x7FF0000000000000972; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float 0x7FF8000000000000973; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[TMP9]], i64 0974; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[R0]], i64 1975; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[R1]], i64 1976; CHECK-NEXT: [[AX12:%.*]] = call float @llvm.fabs.f32(float [[TMP11]])977; CHECK-NEXT: [[AY13:%.*]] = call float @llvm.fabs.f32(float [[TMP12]])978; CHECK-NEXT: [[TMP13:%.*]] = fcmp ogt float [[AX12]], [[AY13]]979; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE46:.*]], label %[[FREM_ELSE47:.*]]980; CHECK: [[BB14:.*]]:981; CHECK-NEXT: [[RET14:%.*]] = phi float [ [[TMP101:%.*]], %[[FREM_LOOP_EXIT55:.*]] ], [ [[TMP93:%.*]], %[[FREM_ELSE47]] ]982; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq float [[TMP12]], 0.000000e+00983; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], float 0x7FF8000000000000, float [[RET14]]984; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.fabs.f32(float [[TMP11]])985; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult float [[TMP17]], 0x7FF0000000000000986; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float 0x7FF8000000000000987; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP19]], i64 1988; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x float> [[R0]], i64 2989; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[R1]], i64 2990; CHECK-NEXT: [[AX43:%.*]] = call float @llvm.fabs.f32(float [[TMP21]])991; CHECK-NEXT: [[AY44:%.*]] = call float @llvm.fabs.f32(float [[TMP22]])992; CHECK-NEXT: [[TMP23:%.*]] = fcmp ogt float [[AX43]], [[AY44]]993; CHECK-NEXT: br i1 [[TMP23]], label %[[FREM_COMPUTE15:.*]], label %[[FREM_ELSE16:.*]]994; CHECK: [[BB24:.*]]:995; CHECK-NEXT: [[RET45:%.*]] = phi float [ [[TMP83:%.*]], %[[FREM_LOOP_EXIT24:.*]] ], [ [[TMP75:%.*]], %[[FREM_ELSE16]] ]996; CHECK-NEXT: [[TMP25:%.*]] = fcmp ueq float [[TMP22]], 0.000000e+00997; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], float 0x7FF8000000000000, float [[RET45]]998; CHECK-NEXT: [[TMP27:%.*]] = call float @llvm.fabs.f32(float [[TMP21]])999; CHECK-NEXT: [[TMP28:%.*]] = fcmp ult float [[TMP27]], 0x7FF00000000000001000; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], float [[TMP26]], float 0x7FF80000000000001001; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x float> [[TMP20]], float [[TMP29]], i64 21002; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x float> [[R0]], i64 31003; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x float> [[R1]], i64 31004; CHECK-NEXT: [[AX74:%.*]] = call float @llvm.fabs.f32(float [[TMP31]])1005; CHECK-NEXT: [[AY75:%.*]] = call float @llvm.fabs.f32(float [[TMP32]])1006; CHECK-NEXT: [[TMP33:%.*]] = fcmp ogt float [[AX74]], [[AY75]]1007; CHECK-NEXT: br i1 [[TMP33]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]1008; CHECK: [[BB34:.*]]:1009; CHECK-NEXT: [[RET76:%.*]] = phi float [ [[TMP65:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP57:%.*]], %[[FREM_ELSE]] ]1010; CHECK-NEXT: [[TMP35:%.*]] = fcmp ueq float [[TMP32]], 0.000000e+001011; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], float 0x7FF8000000000000, float [[RET76]]1012; CHECK-NEXT: [[TMP37:%.*]] = call float @llvm.fabs.f32(float [[TMP31]])1013; CHECK-NEXT: [[TMP38:%.*]] = fcmp ult float [[TMP37]], 0x7FF00000000000001014; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], float [[TMP36]], float 0x7FF80000000000001015; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x float> [[TMP30]], float [[TMP39]], i64 31016; CHECK-NEXT: store <4 x float> [[R2]], ptr addrspace(1) [[OUT]], align 161017; CHECK-NEXT: ret void1018; CHECK: [[FREM_COMPUTE]]:1019; CHECK-NEXT: [[TMP40:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX74]])1020; CHECK-NEXT: [[TMP41:%.*]] = extractvalue { float, i32 } [[TMP40]], 01021; CHECK-NEXT: [[TMP42:%.*]] = extractvalue { float, i32 } [[TMP40]], 11022; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP42]], 11023; CHECK-NEXT: [[AX1:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP41]], i32 12)1024; CHECK-NEXT: [[TMP43:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY75]])1025; CHECK-NEXT: [[TMP44:%.*]] = extractvalue { float, i32 } [[TMP43]], 01026; CHECK-NEXT: [[TMP45:%.*]] = extractvalue { float, i32 } [[TMP43]], 11027; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP45]], 11028; CHECK-NEXT: [[AY2:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP44]], i32 1)1029; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]1030; CHECK-NEXT: [[AYINV:%.*]] = fdiv float 1.000000e+00, [[AY2]]1031; CHECK-NEXT: [[TMP46:%.*]] = icmp sgt i32 [[NB]], 121032; CHECK-NEXT: br i1 [[TMP46]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]1033; CHECK: [[FREM_ELSE]]:1034; CHECK-NEXT: [[TMP48:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP31]])1035; CHECK-NEXT: [[TMP49:%.*]] = fcmp oeq float [[AX74]], [[AY75]]1036; CHECK-NEXT: [[TMP57]] = select i1 [[TMP49]], float [[TMP48]], float [[TMP31]]1037; CHECK-NEXT: br label %[[BB34]]1038; CHECK: [[FREM_LOOP_BODY]]:1039; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]1040; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi float [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]1041; CHECK-NEXT: [[TMP50:%.*]] = fmul float [[AX_LOOP_PHI]], [[AYINV]]1042; CHECK-NEXT: [[Q:%.*]] = call float @llvm.rint.f32(float [[TMP50]])1043; CHECK-NEXT: [[TMP51:%.*]] = fneg float [[Q]]1044; CHECK-NEXT: [[AX3:%.*]] = call float @llvm.fma.f32(float [[TMP51]], float [[AY2]], float [[AX_LOOP_PHI]])1045; CHECK-NEXT: [[CLT:%.*]] = fcmp olt float [[AX3]], 0.000000e+001046; CHECK-NEXT: [[AXP:%.*]] = fadd float [[AX3]], [[AY2]]1047; CHECK-NEXT: [[AX4:%.*]] = select i1 [[CLT]], float [[AXP]], float [[AX3]]1048; CHECK-NEXT: [[AX_UPDATE]] = call float @llvm.ldexp.f32.i32(float [[AX4]], i32 12)1049; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 121050; CHECK-NEXT: [[TMP52:%.*]] = icmp sgt i32 [[NB_IV]], 121051; CHECK-NEXT: br i1 [[TMP52]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]1052; CHECK: [[FREM_LOOP_EXIT]]:1053; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi float [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]1054; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]1055; CHECK-NEXT: [[TMP53:%.*]] = sub i32 [[NB_EXIT_PHI]], 121056; CHECK-NEXT: [[TMP54:%.*]] = add i32 [[TMP53]], 11057; CHECK-NEXT: [[AX5:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI]], i32 [[TMP54]])1058; CHECK-NEXT: [[TMP55:%.*]] = fmul float [[AX5]], [[AYINV]]1059; CHECK-NEXT: [[Q6:%.*]] = call float @llvm.rint.f32(float [[TMP55]])1060; CHECK-NEXT: [[TMP56:%.*]] = fneg float [[Q6]]1061; CHECK-NEXT: [[AX7:%.*]] = call float @llvm.fma.f32(float [[TMP56]], float [[AY2]], float [[AX5]])1062; CHECK-NEXT: [[CLT8:%.*]] = fcmp olt float [[AX7]], 0.000000e+001063; CHECK-NEXT: [[AXP9:%.*]] = fadd float [[AX7]], [[AY2]]1064; CHECK-NEXT: [[AX10:%.*]] = select i1 [[CLT8]], float [[AXP9]], float [[AX7]]1065; CHECK-NEXT: [[AX11:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX10]], i32 [[EY]])1066; CHECK-NEXT: [[TMP65]] = call float @llvm.copysign.f32(float [[AX11]], float [[TMP31]])1067; CHECK-NEXT: br label %[[BB34]]1068; CHECK: [[FREM_COMPUTE15]]:1069; CHECK-NEXT: [[TMP58:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX43]])1070; CHECK-NEXT: [[TMP59:%.*]] = extractvalue { float, i32 } [[TMP58]], 01071; CHECK-NEXT: [[TMP60:%.*]] = extractvalue { float, i32 } [[TMP58]], 11072; CHECK-NEXT: [[EX17:%.*]] = sub i32 [[TMP60]], 11073; CHECK-NEXT: [[AX18:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP59]], i32 12)1074; CHECK-NEXT: [[TMP61:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY44]])1075; CHECK-NEXT: [[TMP62:%.*]] = extractvalue { float, i32 } [[TMP61]], 01076; CHECK-NEXT: [[TMP63:%.*]] = extractvalue { float, i32 } [[TMP61]], 11077; CHECK-NEXT: [[EY19:%.*]] = sub i32 [[TMP63]], 11078; CHECK-NEXT: [[AY20:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP62]], i32 1)1079; CHECK-NEXT: [[NB21:%.*]] = sub i32 [[EX17]], [[EY19]]1080; CHECK-NEXT: [[AYINV22:%.*]] = fdiv float 1.000000e+00, [[AY20]]1081; CHECK-NEXT: [[TMP64:%.*]] = icmp sgt i32 [[NB21]], 121082; CHECK-NEXT: br i1 [[TMP64]], label %[[FREM_LOOP_BODY23:.*]], label %[[FREM_LOOP_EXIT24]]1083; CHECK: [[FREM_ELSE16]]:1084; CHECK-NEXT: [[TMP66:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP21]])1085; CHECK-NEXT: [[TMP67:%.*]] = fcmp oeq float [[AX43]], [[AY44]]1086; CHECK-NEXT: [[TMP75]] = select i1 [[TMP67]], float [[TMP66]], float [[TMP21]]1087; CHECK-NEXT: br label %[[BB24]]1088; CHECK: [[FREM_LOOP_BODY23]]:1089; CHECK-NEXT: [[NB_IV25:%.*]] = phi i32 [ [[NB21]], %[[FREM_COMPUTE15]] ], [ [[NB_UPDATE33:%.*]], %[[FREM_LOOP_BODY23]] ]1090; CHECK-NEXT: [[AX_LOOP_PHI26:%.*]] = phi float [ [[AX18]], %[[FREM_COMPUTE15]] ], [ [[AX_UPDATE32:%.*]], %[[FREM_LOOP_BODY23]] ]1091; CHECK-NEXT: [[TMP68:%.*]] = fmul float [[AX_LOOP_PHI26]], [[AYINV22]]1092; CHECK-NEXT: [[Q27:%.*]] = call float @llvm.rint.f32(float [[TMP68]])1093; CHECK-NEXT: [[TMP69:%.*]] = fneg float [[Q27]]1094; CHECK-NEXT: [[AX28:%.*]] = call float @llvm.fma.f32(float [[TMP69]], float [[AY20]], float [[AX_LOOP_PHI26]])1095; CHECK-NEXT: [[CLT29:%.*]] = fcmp olt float [[AX28]], 0.000000e+001096; CHECK-NEXT: [[AXP30:%.*]] = fadd float [[AX28]], [[AY20]]1097; CHECK-NEXT: [[AX31:%.*]] = select i1 [[CLT29]], float [[AXP30]], float [[AX28]]1098; CHECK-NEXT: [[AX_UPDATE32]] = call float @llvm.ldexp.f32.i32(float [[AX31]], i32 12)1099; CHECK-NEXT: [[NB_UPDATE33]] = sub i32 [[NB_IV25]], 121100; CHECK-NEXT: [[TMP70:%.*]] = icmp sgt i32 [[NB_IV25]], 121101; CHECK-NEXT: br i1 [[TMP70]], label %[[FREM_LOOP_BODY23]], label %[[FREM_LOOP_EXIT24]]1102; CHECK: [[FREM_LOOP_EXIT24]]:1103; CHECK-NEXT: [[AX_EXIT_PHI34:%.*]] = phi float [ [[AX18]], %[[FREM_COMPUTE15]] ], [ [[AX_LOOP_PHI26]], %[[FREM_LOOP_BODY23]] ]1104; CHECK-NEXT: [[NB_EXIT_PHI35:%.*]] = phi i32 [ [[NB_IV25]], %[[FREM_LOOP_BODY23]] ], [ [[NB21]], %[[FREM_COMPUTE15]] ]1105; CHECK-NEXT: [[TMP71:%.*]] = sub i32 [[NB_EXIT_PHI35]], 121106; CHECK-NEXT: [[TMP72:%.*]] = add i32 [[TMP71]], 11107; CHECK-NEXT: [[AX36:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI34]], i32 [[TMP72]])1108; CHECK-NEXT: [[TMP73:%.*]] = fmul float [[AX36]], [[AYINV22]]1109; CHECK-NEXT: [[Q37:%.*]] = call float @llvm.rint.f32(float [[TMP73]])1110; CHECK-NEXT: [[TMP74:%.*]] = fneg float [[Q37]]1111; CHECK-NEXT: [[AX38:%.*]] = call float @llvm.fma.f32(float [[TMP74]], float [[AY20]], float [[AX36]])1112; CHECK-NEXT: [[CLT39:%.*]] = fcmp olt float [[AX38]], 0.000000e+001113; CHECK-NEXT: [[AXP40:%.*]] = fadd float [[AX38]], [[AY20]]1114; CHECK-NEXT: [[AX41:%.*]] = select i1 [[CLT39]], float [[AXP40]], float [[AX38]]1115; CHECK-NEXT: [[AX42:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX41]], i32 [[EY19]])1116; CHECK-NEXT: [[TMP83]] = call float @llvm.copysign.f32(float [[AX42]], float [[TMP21]])1117; CHECK-NEXT: br label %[[BB24]]1118; CHECK: [[FREM_COMPUTE46]]:1119; CHECK-NEXT: [[TMP76:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX12]])1120; CHECK-NEXT: [[TMP77:%.*]] = extractvalue { float, i32 } [[TMP76]], 01121; CHECK-NEXT: [[TMP78:%.*]] = extractvalue { float, i32 } [[TMP76]], 11122; CHECK-NEXT: [[EX48:%.*]] = sub i32 [[TMP78]], 11123; CHECK-NEXT: [[AX49:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP77]], i32 12)1124; CHECK-NEXT: [[TMP79:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY13]])1125; CHECK-NEXT: [[TMP80:%.*]] = extractvalue { float, i32 } [[TMP79]], 01126; CHECK-NEXT: [[TMP81:%.*]] = extractvalue { float, i32 } [[TMP79]], 11127; CHECK-NEXT: [[EY50:%.*]] = sub i32 [[TMP81]], 11128; CHECK-NEXT: [[AY51:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP80]], i32 1)1129; CHECK-NEXT: [[NB52:%.*]] = sub i32 [[EX48]], [[EY50]]1130; CHECK-NEXT: [[AYINV53:%.*]] = fdiv float 1.000000e+00, [[AY51]]1131; CHECK-NEXT: [[TMP82:%.*]] = icmp sgt i32 [[NB52]], 121132; CHECK-NEXT: br i1 [[TMP82]], label %[[FREM_LOOP_BODY54:.*]], label %[[FREM_LOOP_EXIT55]]1133; CHECK: [[FREM_ELSE47]]:1134; CHECK-NEXT: [[TMP84:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP11]])1135; CHECK-NEXT: [[TMP85:%.*]] = fcmp oeq float [[AX12]], [[AY13]]1136; CHECK-NEXT: [[TMP93]] = select i1 [[TMP85]], float [[TMP84]], float [[TMP11]]1137; CHECK-NEXT: br label %[[BB14]]1138; CHECK: [[FREM_LOOP_BODY54]]:1139; CHECK-NEXT: [[NB_IV56:%.*]] = phi i32 [ [[NB52]], %[[FREM_COMPUTE46]] ], [ [[NB_UPDATE64:%.*]], %[[FREM_LOOP_BODY54]] ]1140; CHECK-NEXT: [[AX_LOOP_PHI57:%.*]] = phi float [ [[AX49]], %[[FREM_COMPUTE46]] ], [ [[AX_UPDATE63:%.*]], %[[FREM_LOOP_BODY54]] ]1141; CHECK-NEXT: [[TMP86:%.*]] = fmul float [[AX_LOOP_PHI57]], [[AYINV53]]1142; CHECK-NEXT: [[Q58:%.*]] = call float @llvm.rint.f32(float [[TMP86]])1143; CHECK-NEXT: [[TMP87:%.*]] = fneg float [[Q58]]1144; CHECK-NEXT: [[AX59:%.*]] = call float @llvm.fma.f32(float [[TMP87]], float [[AY51]], float [[AX_LOOP_PHI57]])1145; CHECK-NEXT: [[CLT60:%.*]] = fcmp olt float [[AX59]], 0.000000e+001146; CHECK-NEXT: [[AXP61:%.*]] = fadd float [[AX59]], [[AY51]]1147; CHECK-NEXT: [[AX62:%.*]] = select i1 [[CLT60]], float [[AXP61]], float [[AX59]]1148; CHECK-NEXT: [[AX_UPDATE63]] = call float @llvm.ldexp.f32.i32(float [[AX62]], i32 12)1149; CHECK-NEXT: [[NB_UPDATE64]] = sub i32 [[NB_IV56]], 121150; CHECK-NEXT: [[TMP88:%.*]] = icmp sgt i32 [[NB_IV56]], 121151; CHECK-NEXT: br i1 [[TMP88]], label %[[FREM_LOOP_BODY54]], label %[[FREM_LOOP_EXIT55]]1152; CHECK: [[FREM_LOOP_EXIT55]]:1153; CHECK-NEXT: [[AX_EXIT_PHI65:%.*]] = phi float [ [[AX49]], %[[FREM_COMPUTE46]] ], [ [[AX_LOOP_PHI57]], %[[FREM_LOOP_BODY54]] ]1154; CHECK-NEXT: [[NB_EXIT_PHI66:%.*]] = phi i32 [ [[NB_IV56]], %[[FREM_LOOP_BODY54]] ], [ [[NB52]], %[[FREM_COMPUTE46]] ]1155; CHECK-NEXT: [[TMP89:%.*]] = sub i32 [[NB_EXIT_PHI66]], 121156; CHECK-NEXT: [[TMP90:%.*]] = add i32 [[TMP89]], 11157; CHECK-NEXT: [[AX67:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI65]], i32 [[TMP90]])1158; CHECK-NEXT: [[TMP91:%.*]] = fmul float [[AX67]], [[AYINV53]]1159; CHECK-NEXT: [[Q68:%.*]] = call float @llvm.rint.f32(float [[TMP91]])1160; CHECK-NEXT: [[TMP92:%.*]] = fneg float [[Q68]]1161; CHECK-NEXT: [[AX69:%.*]] = call float @llvm.fma.f32(float [[TMP92]], float [[AY51]], float [[AX67]])1162; CHECK-NEXT: [[CLT70:%.*]] = fcmp olt float [[AX69]], 0.000000e+001163; CHECK-NEXT: [[AXP71:%.*]] = fadd float [[AX69]], [[AY51]]1164; CHECK-NEXT: [[AX72:%.*]] = select i1 [[CLT70]], float [[AXP71]], float [[AX69]]1165; CHECK-NEXT: [[AX73:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX72]], i32 [[EY50]])1166; CHECK-NEXT: [[TMP101]] = call float @llvm.copysign.f32(float [[AX73]], float [[TMP11]])1167; CHECK-NEXT: br label %[[BB14]]1168; CHECK: [[FREM_COMPUTE77]]:1169; CHECK-NEXT: [[TMP94:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AX]])1170; CHECK-NEXT: [[TMP95:%.*]] = extractvalue { float, i32 } [[TMP94]], 01171; CHECK-NEXT: [[TMP96:%.*]] = extractvalue { float, i32 } [[TMP94]], 11172; CHECK-NEXT: [[EX79:%.*]] = sub i32 [[TMP96]], 11173; CHECK-NEXT: [[AX80:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP95]], i32 12)1174; CHECK-NEXT: [[TMP97:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[AY]])1175; CHECK-NEXT: [[TMP98:%.*]] = extractvalue { float, i32 } [[TMP97]], 01176; CHECK-NEXT: [[TMP99:%.*]] = extractvalue { float, i32 } [[TMP97]], 11177; CHECK-NEXT: [[EY81:%.*]] = sub i32 [[TMP99]], 11178; CHECK-NEXT: [[AY82:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP98]], i32 1)1179; CHECK-NEXT: [[NB83:%.*]] = sub i32 [[EX79]], [[EY81]]1180; CHECK-NEXT: [[AYINV84:%.*]] = fdiv float 1.000000e+00, [[AY82]]1181; CHECK-NEXT: [[TMP100:%.*]] = icmp sgt i32 [[NB83]], 121182; CHECK-NEXT: br i1 [[TMP100]], label %[[FREM_LOOP_BODY85:.*]], label %[[FREM_LOOP_EXIT86]]1183; CHECK: [[FREM_ELSE78]]:1184; CHECK-NEXT: [[TMP102:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP1]])1185; CHECK-NEXT: [[TMP103:%.*]] = fcmp oeq float [[AX]], [[AY]]1186; CHECK-NEXT: [[TMP111]] = select i1 [[TMP103]], float [[TMP102]], float [[TMP1]]1187; CHECK-NEXT: br label %[[BB4]]1188; CHECK: [[FREM_LOOP_BODY85]]:1189; CHECK-NEXT: [[NB_IV87:%.*]] = phi i32 [ [[NB83]], %[[FREM_COMPUTE77]] ], [ [[NB_UPDATE95:%.*]], %[[FREM_LOOP_BODY85]] ]1190; CHECK-NEXT: [[AX_LOOP_PHI88:%.*]] = phi float [ [[AX80]], %[[FREM_COMPUTE77]] ], [ [[AX_UPDATE94:%.*]], %[[FREM_LOOP_BODY85]] ]1191; CHECK-NEXT: [[TMP104:%.*]] = fmul float [[AX_LOOP_PHI88]], [[AYINV84]]1192; CHECK-NEXT: [[Q89:%.*]] = call float @llvm.rint.f32(float [[TMP104]])1193; CHECK-NEXT: [[TMP105:%.*]] = fneg float [[Q89]]1194; CHECK-NEXT: [[AX90:%.*]] = call float @llvm.fma.f32(float [[TMP105]], float [[AY82]], float [[AX_LOOP_PHI88]])1195; CHECK-NEXT: [[CLT91:%.*]] = fcmp olt float [[AX90]], 0.000000e+001196; CHECK-NEXT: [[AXP92:%.*]] = fadd float [[AX90]], [[AY82]]1197; CHECK-NEXT: [[AX93:%.*]] = select i1 [[CLT91]], float [[AXP92]], float [[AX90]]1198; CHECK-NEXT: [[AX_UPDATE94]] = call float @llvm.ldexp.f32.i32(float [[AX93]], i32 12)1199; CHECK-NEXT: [[NB_UPDATE95]] = sub i32 [[NB_IV87]], 121200; CHECK-NEXT: [[TMP106:%.*]] = icmp sgt i32 [[NB_IV87]], 121201; CHECK-NEXT: br i1 [[TMP106]], label %[[FREM_LOOP_BODY85]], label %[[FREM_LOOP_EXIT86]]1202; CHECK: [[FREM_LOOP_EXIT86]]:1203; CHECK-NEXT: [[AX_EXIT_PHI96:%.*]] = phi float [ [[AX80]], %[[FREM_COMPUTE77]] ], [ [[AX_LOOP_PHI88]], %[[FREM_LOOP_BODY85]] ]1204; CHECK-NEXT: [[NB_EXIT_PHI97:%.*]] = phi i32 [ [[NB_IV87]], %[[FREM_LOOP_BODY85]] ], [ [[NB83]], %[[FREM_COMPUTE77]] ]1205; CHECK-NEXT: [[TMP107:%.*]] = sub i32 [[NB_EXIT_PHI97]], 121206; CHECK-NEXT: [[TMP108:%.*]] = add i32 [[TMP107]], 11207; CHECK-NEXT: [[AX98:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX_EXIT_PHI96]], i32 [[TMP108]])1208; CHECK-NEXT: [[TMP109:%.*]] = fmul float [[AX98]], [[AYINV84]]1209; CHECK-NEXT: [[Q99:%.*]] = call float @llvm.rint.f32(float [[TMP109]])1210; CHECK-NEXT: [[TMP110:%.*]] = fneg float [[Q99]]1211; CHECK-NEXT: [[AX100:%.*]] = call float @llvm.fma.f32(float [[TMP110]], float [[AY82]], float [[AX98]])1212; CHECK-NEXT: [[CLT101:%.*]] = fcmp olt float [[AX100]], 0.000000e+001213; CHECK-NEXT: [[AXP102:%.*]] = fadd float [[AX100]], [[AY82]]1214; CHECK-NEXT: [[AX103:%.*]] = select i1 [[CLT101]], float [[AXP102]], float [[AX100]]1215; CHECK-NEXT: [[AX104:%.*]] = call float @llvm.ldexp.f32.i32(float [[AX103]], i32 [[EY81]])1216; CHECK-NEXT: [[TMP112]] = call float @llvm.copysign.f32(float [[AX104]], float [[TMP1]])1217; CHECK-NEXT: br label %[[BB4]]1218;1219 ptr addrspace(1) %in2) {1220 %gep2 = getelementptr <4 x float>, ptr addrspace(1) %in2, i32 41221 %r0 = load <4 x float>, ptr addrspace(1) %in1, align 161222 %r1 = load <4 x float>, ptr addrspace(1) %gep2, align 161223 %r2 = frem <4 x float> %r0, %r11224 store <4 x float> %r2, ptr addrspace(1) %out, align 161225 ret void1226}1227 1228define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,1229; CHECK-LABEL: define amdgpu_kernel void @frem_v2f64(1230; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[IN1:%.*]], ptr addrspace(1) [[IN2:%.*]]) {1231; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <2 x double>, ptr addrspace(1) [[IN2]], i32 41232; CHECK-NEXT: [[R0:%.*]] = load <2 x double>, ptr addrspace(1) [[IN1]], align 161233; CHECK-NEXT: [[R1:%.*]] = load <2 x double>, ptr addrspace(1) [[GEP2]], align 161234; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[R0]], i64 01235; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[R1]], i64 01236; CHECK-NEXT: [[AX:%.*]] = call double @llvm.fabs.f64(double [[TMP1]])1237; CHECK-NEXT: [[AY:%.*]] = call double @llvm.fabs.f64(double [[TMP2]])1238; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt double [[AX]], [[AY]]1239; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE15:.*]], label %[[FREM_ELSE16:.*]]1240; CHECK: [[BB4:.*]]:1241; CHECK-NEXT: [[RET:%.*]] = phi double [ [[TMP56:%.*]], %[[FREM_LOOP_EXIT24:.*]] ], [ [[TMP55:%.*]], %[[FREM_ELSE16]] ]1242; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq double [[TMP2]], 0.000000e+001243; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double 0x7FF8000000000000, double [[RET]]1244; CHECK-NEXT: [[TMP7:%.*]] = call double @llvm.fabs.f64(double [[TMP1]])1245; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult double [[TMP7]], 0x7FF00000000000001246; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], double [[TMP6]], double 0x7FF80000000000001247; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> poison, double [[TMP9]], i64 01248; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[R0]], i64 11249; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[R1]], i64 11250; CHECK-NEXT: [[AX12:%.*]] = call double @llvm.fabs.f64(double [[TMP11]])1251; CHECK-NEXT: [[AY13:%.*]] = call double @llvm.fabs.f64(double [[TMP12]])1252; CHECK-NEXT: [[TMP13:%.*]] = fcmp ogt double [[AX12]], [[AY13]]1253; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]1254; CHECK: [[BB14:.*]]:1255; CHECK-NEXT: [[RET14:%.*]] = phi double [ [[TMP45:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP37:%.*]], %[[FREM_ELSE]] ]1256; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq double [[TMP12]], 0.000000e+001257; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], double 0x7FF8000000000000, double [[RET14]]1258; CHECK-NEXT: [[TMP17:%.*]] = call double @llvm.fabs.f64(double [[TMP11]])1259; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult double [[TMP17]], 0x7FF00000000000001260; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], double [[TMP16]], double 0x7FF80000000000001261; CHECK-NEXT: [[R2:%.*]] = insertelement <2 x double> [[TMP10]], double [[TMP19]], i64 11262; CHECK-NEXT: store <2 x double> [[R2]], ptr addrspace(1) [[OUT]], align 161263; CHECK-NEXT: ret void1264; CHECK: [[FREM_COMPUTE]]:1265; CHECK-NEXT: [[TMP20:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[AX12]])1266; CHECK-NEXT: [[TMP21:%.*]] = extractvalue { double, i32 } [[TMP20]], 01267; CHECK-NEXT: [[TMP22:%.*]] = extractvalue { double, i32 } [[TMP20]], 11268; CHECK-NEXT: [[EX:%.*]] = sub i32 [[TMP22]], 11269; CHECK-NEXT: [[AX1:%.*]] = call double @llvm.ldexp.f64.i32(double [[TMP21]], i32 26)1270; CHECK-NEXT: [[TMP23:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[AY13]])1271; CHECK-NEXT: [[TMP24:%.*]] = extractvalue { double, i32 } [[TMP23]], 01272; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { double, i32 } [[TMP23]], 11273; CHECK-NEXT: [[EY:%.*]] = sub i32 [[TMP25]], 11274; CHECK-NEXT: [[AY2:%.*]] = call double @llvm.ldexp.f64.i32(double [[TMP24]], i32 1)1275; CHECK-NEXT: [[NB:%.*]] = sub i32 [[EX]], [[EY]]1276; CHECK-NEXT: [[AYINV:%.*]] = fdiv double 1.000000e+00, [[AY2]]1277; CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i32 [[NB]], 261278; CHECK-NEXT: br i1 [[TMP26]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]1279; CHECK: [[FREM_ELSE]]:1280; CHECK-NEXT: [[TMP28:%.*]] = call double @llvm.copysign.f64(double 0.000000e+00, double [[TMP11]])1281; CHECK-NEXT: [[TMP29:%.*]] = fcmp oeq double [[AX12]], [[AY13]]1282; CHECK-NEXT: [[TMP37]] = select i1 [[TMP29]], double [[TMP28]], double [[TMP11]]1283; CHECK-NEXT: br label %[[BB14]]1284; CHECK: [[FREM_LOOP_BODY]]:1285; CHECK-NEXT: [[NB_IV:%.*]] = phi i32 [ [[NB]], %[[FREM_COMPUTE]] ], [ [[NB_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]1286; CHECK-NEXT: [[AX_LOOP_PHI:%.*]] = phi double [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_UPDATE:%.*]], %[[FREM_LOOP_BODY]] ]1287; CHECK-NEXT: [[TMP30:%.*]] = fmul double [[AX_LOOP_PHI]], [[AYINV]]1288; CHECK-NEXT: [[Q:%.*]] = call double @llvm.rint.f64(double [[TMP30]])1289; CHECK-NEXT: [[TMP31:%.*]] = fneg double [[Q]]1290; CHECK-NEXT: [[AX3:%.*]] = call double @llvm.fma.f64(double [[TMP31]], double [[AY2]], double [[AX_LOOP_PHI]])1291; CHECK-NEXT: [[CLT:%.*]] = fcmp olt double [[AX3]], 0.000000e+001292; CHECK-NEXT: [[AXP:%.*]] = fadd double [[AX3]], [[AY2]]1293; CHECK-NEXT: [[AX4:%.*]] = select i1 [[CLT]], double [[AXP]], double [[AX3]]1294; CHECK-NEXT: [[AX_UPDATE]] = call double @llvm.ldexp.f64.i32(double [[AX4]], i32 26)1295; CHECK-NEXT: [[NB_UPDATE]] = sub i32 [[NB_IV]], 261296; CHECK-NEXT: [[TMP32:%.*]] = icmp sgt i32 [[NB_IV]], 261297; CHECK-NEXT: br i1 [[TMP32]], label %[[FREM_LOOP_BODY]], label %[[FREM_LOOP_EXIT]]1298; CHECK: [[FREM_LOOP_EXIT]]:1299; CHECK-NEXT: [[AX_EXIT_PHI:%.*]] = phi double [ [[AX1]], %[[FREM_COMPUTE]] ], [ [[AX_LOOP_PHI]], %[[FREM_LOOP_BODY]] ]1300; CHECK-NEXT: [[NB_EXIT_PHI:%.*]] = phi i32 [ [[NB_IV]], %[[FREM_LOOP_BODY]] ], [ [[NB]], %[[FREM_COMPUTE]] ]1301; CHECK-NEXT: [[TMP33:%.*]] = sub i32 [[NB_EXIT_PHI]], 261302; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], 11303; CHECK-NEXT: [[AX5:%.*]] = call double @llvm.ldexp.f64.i32(double [[AX_EXIT_PHI]], i32 [[TMP34]])1304; CHECK-NEXT: [[TMP35:%.*]] = fmul double [[AX5]], [[AYINV]]1305; CHECK-NEXT: [[Q6:%.*]] = call double @llvm.rint.f64(double [[TMP35]])1306; CHECK-NEXT: [[TMP36:%.*]] = fneg double [[Q6]]1307; CHECK-NEXT: [[AX7:%.*]] = call double @llvm.fma.f64(double [[TMP36]], double [[AY2]], double [[AX5]])1308; CHECK-NEXT: [[CLT8:%.*]] = fcmp olt double [[AX7]], 0.000000e+001309; CHECK-NEXT: [[AXP9:%.*]] = fadd double [[AX7]], [[AY2]]1310; CHECK-NEXT: [[AX10:%.*]] = select i1 [[CLT8]], double [[AXP9]], double [[AX7]]1311; CHECK-NEXT: [[AX11:%.*]] = call double @llvm.ldexp.f64.i32(double [[AX10]], i32 [[EY]])1312; CHECK-NEXT: [[TMP45]] = call double @llvm.copysign.f64(double [[AX11]], double [[TMP11]])1313; CHECK-NEXT: br label %[[BB14]]1314; CHECK: [[FREM_COMPUTE15]]:1315; CHECK-NEXT: [[TMP38:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[AX]])1316; CHECK-NEXT: [[TMP39:%.*]] = extractvalue { double, i32 } [[TMP38]], 01317; CHECK-NEXT: [[TMP40:%.*]] = extractvalue { double, i32 } [[TMP38]], 11318; CHECK-NEXT: [[EX17:%.*]] = sub i32 [[TMP40]], 11319; CHECK-NEXT: [[AX18:%.*]] = call double @llvm.ldexp.f64.i32(double [[TMP39]], i32 26)1320; CHECK-NEXT: [[TMP41:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[AY]])1321; CHECK-NEXT: [[TMP42:%.*]] = extractvalue { double, i32 } [[TMP41]], 01322; CHECK-NEXT: [[TMP43:%.*]] = extractvalue { double, i32 } [[TMP41]], 11323; CHECK-NEXT: [[EY19:%.*]] = sub i32 [[TMP43]], 11324; CHECK-NEXT: [[AY20:%.*]] = call double @llvm.ldexp.f64.i32(double [[TMP42]], i32 1)1325; CHECK-NEXT: [[NB21:%.*]] = sub i32 [[EX17]], [[EY19]]1326; CHECK-NEXT: [[AYINV22:%.*]] = fdiv double 1.000000e+00, [[AY20]]1327; CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i32 [[NB21]], 261328; CHECK-NEXT: br i1 [[TMP44]], label %[[FREM_LOOP_BODY23:.*]], label %[[FREM_LOOP_EXIT24]]1329; CHECK: [[FREM_ELSE16]]:1330; CHECK-NEXT: [[TMP46:%.*]] = call double @llvm.copysign.f64(double 0.000000e+00, double [[TMP1]])1331; CHECK-NEXT: [[TMP47:%.*]] = fcmp oeq double [[AX]], [[AY]]1332; CHECK-NEXT: [[TMP55]] = select i1 [[TMP47]], double [[TMP46]], double [[TMP1]]1333; CHECK-NEXT: br label %[[BB4]]1334; CHECK: [[FREM_LOOP_BODY23]]:1335; CHECK-NEXT: [[NB_IV25:%.*]] = phi i32 [ [[NB21]], %[[FREM_COMPUTE15]] ], [ [[NB_UPDATE33:%.*]], %[[FREM_LOOP_BODY23]] ]1336; CHECK-NEXT: [[AX_LOOP_PHI26:%.*]] = phi double [ [[AX18]], %[[FREM_COMPUTE15]] ], [ [[AX_UPDATE32:%.*]], %[[FREM_LOOP_BODY23]] ]1337; CHECK-NEXT: [[TMP48:%.*]] = fmul double [[AX_LOOP_PHI26]], [[AYINV22]]1338; CHECK-NEXT: [[Q27:%.*]] = call double @llvm.rint.f64(double [[TMP48]])1339; CHECK-NEXT: [[TMP49:%.*]] = fneg double [[Q27]]1340; CHECK-NEXT: [[AX28:%.*]] = call double @llvm.fma.f64(double [[TMP49]], double [[AY20]], double [[AX_LOOP_PHI26]])1341; CHECK-NEXT: [[CLT29:%.*]] = fcmp olt double [[AX28]], 0.000000e+001342; CHECK-NEXT: [[AXP30:%.*]] = fadd double [[AX28]], [[AY20]]1343; CHECK-NEXT: [[AX31:%.*]] = select i1 [[CLT29]], double [[AXP30]], double [[AX28]]1344; CHECK-NEXT: [[AX_UPDATE32]] = call double @llvm.ldexp.f64.i32(double [[AX31]], i32 26)1345; CHECK-NEXT: [[NB_UPDATE33]] = sub i32 [[NB_IV25]], 261346; CHECK-NEXT: [[TMP50:%.*]] = icmp sgt i32 [[NB_IV25]], 261347; CHECK-NEXT: br i1 [[TMP50]], label %[[FREM_LOOP_BODY23]], label %[[FREM_LOOP_EXIT24]]1348; CHECK: [[FREM_LOOP_EXIT24]]:1349; CHECK-NEXT: [[AX_EXIT_PHI34:%.*]] = phi double [ [[AX18]], %[[FREM_COMPUTE15]] ], [ [[AX_LOOP_PHI26]], %[[FREM_LOOP_BODY23]] ]1350; CHECK-NEXT: [[NB_EXIT_PHI35:%.*]] = phi i32 [ [[NB_IV25]], %[[FREM_LOOP_BODY23]] ], [ [[NB21]], %[[FREM_COMPUTE15]] ]1351; CHECK-NEXT: [[TMP51:%.*]] = sub i32 [[NB_EXIT_PHI35]], 261352; CHECK-NEXT: [[TMP52:%.*]] = add i32 [[TMP51]], 11353; CHECK-NEXT: [[AX36:%.*]] = call double @llvm.ldexp.f64.i32(double [[AX_EXIT_PHI34]], i32 [[TMP52]])1354; CHECK-NEXT: [[TMP53:%.*]] = fmul double [[AX36]], [[AYINV22]]1355; CHECK-NEXT: [[Q37:%.*]] = call double @llvm.rint.f64(double [[TMP53]])1356; CHECK-NEXT: [[TMP54:%.*]] = fneg double [[Q37]]1357; CHECK-NEXT: [[AX38:%.*]] = call double @llvm.fma.f64(double [[TMP54]], double [[AY20]], double [[AX36]])1358; CHECK-NEXT: [[CLT39:%.*]] = fcmp olt double [[AX38]], 0.000000e+001359; CHECK-NEXT: [[AXP40:%.*]] = fadd double [[AX38]], [[AY20]]1360; CHECK-NEXT: [[AX41:%.*]] = select i1 [[CLT39]], double [[AXP40]], double [[AX38]]1361; CHECK-NEXT: [[AX42:%.*]] = call double @llvm.ldexp.f64.i32(double [[AX41]], i32 [[EY19]])1362; CHECK-NEXT: [[TMP56]] = call double @llvm.copysign.f64(double [[AX42]], double [[TMP1]])1363; CHECK-NEXT: br label %[[BB4]]1364;1365 ptr addrspace(1) %in2) {1366 %gep2 = getelementptr <2 x double>, ptr addrspace(1) %in2, i32 41367 %r0 = load <2 x double>, ptr addrspace(1) %in1, align 161368 %r1 = load <2 x double>, ptr addrspace(1) %gep2, align 161369 %r2 = frem <2 x double> %r0, %r11370 store <2 x double> %r2, ptr addrspace(1) %out, align 161371 ret void1372}1373