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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes='float2int' -S | FileCheck %s -check-prefixes=CHECK,NONE3; RUN: opt < %s -passes='float2int' -S --data-layout="n64" | FileCheck %s -check-prefixes=CHECK,ONLY644; RUN: opt < %s -passes='float2int' -S --data-layout="n8:16:32:64"| FileCheck %s -check-prefixes=CHECK,MULTIPLE5; RUN: opt < %s -passes=float2int -S --data-layout="e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"| FileCheck %s -check-prefixes=CHECK,PR-791586 7;8; Positive tests9;10 11define i16 @simple1(i8 %a) {12; NONE-LABEL: @simple1(13; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i3214; NONE-NEXT: [[T21:%.*]] = add i32 [[TMP1]], 115; NONE-NEXT: [[TMP2:%.*]] = trunc i32 [[T21]] to i1616; NONE-NEXT: ret i16 [[TMP2]]17;18; ONLY64-LABEL: @simple1(19; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i6420; ONLY64-NEXT: [[T21:%.*]] = add i64 [[TMP1]], 121; ONLY64-NEXT: [[TMP2:%.*]] = trunc i64 [[T21]] to i1622; ONLY64-NEXT: ret i16 [[TMP2]]23;24; MULTIPLE-LABEL: @simple1(25; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i1626; MULTIPLE-NEXT: [[T21:%.*]] = add i16 [[TMP1]], 127; MULTIPLE-NEXT: ret i16 [[T21]]28;29; PR-79158-LABEL: @simple1(30; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i1631; PR-79158-NEXT: [[T21:%.*]] = add i16 [[TMP1]], 132; PR-79158-NEXT: ret i16 [[T21]]33;34 %t1 = uitofp i8 %a to float35 %t2 = fadd float %t1, 1.036 %t3 = fptoui float %t2 to i1637 ret i16 %t338}39 40define i8 @simple2(i8 %a) {41; NONE-LABEL: @simple2(42; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i3243; NONE-NEXT: [[T21:%.*]] = sub i32 [[TMP1]], 144; NONE-NEXT: [[TMP2:%.*]] = trunc i32 [[T21]] to i845; NONE-NEXT: ret i8 [[TMP2]]46;47; ONLY64-LABEL: @simple2(48; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i6449; ONLY64-NEXT: [[T21:%.*]] = sub i64 [[TMP1]], 150; ONLY64-NEXT: [[TMP2:%.*]] = trunc i64 [[T21]] to i851; ONLY64-NEXT: ret i8 [[TMP2]]52;53; MULTIPLE-LABEL: @simple2(54; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i1655; MULTIPLE-NEXT: [[T21:%.*]] = sub i16 [[TMP1]], 156; MULTIPLE-NEXT: [[TMP2:%.*]] = trunc i16 [[T21]] to i857; MULTIPLE-NEXT: ret i8 [[TMP2]]58;59; PR-79158-LABEL: @simple2(60; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i1661; PR-79158-NEXT: [[T21:%.*]] = sub i16 [[TMP1]], 162; PR-79158-NEXT: [[TMP2:%.*]] = trunc i16 [[T21]] to i863; PR-79158-NEXT: ret i8 [[TMP2]]64;65 %t1 = uitofp i8 %a to float66 %t2 = fsub float %t1, 1.067 %t3 = fptoui float %t2 to i868 ret i8 %t369}70 71define i32 @simple3(i8 %a) {72; NONE-LABEL: @simple3(73; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i3274; NONE-NEXT: [[T21:%.*]] = sub i32 [[TMP1]], 175; NONE-NEXT: ret i32 [[T21]]76;77; ONLY64-LABEL: @simple3(78; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i6479; ONLY64-NEXT: [[T21:%.*]] = sub i64 [[TMP1]], 180; ONLY64-NEXT: [[TMP2:%.*]] = trunc i64 [[T21]] to i3281; ONLY64-NEXT: ret i32 [[TMP2]]82;83; MULTIPLE-LABEL: @simple3(84; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i1685; MULTIPLE-NEXT: [[T21:%.*]] = sub i16 [[TMP1]], 186; MULTIPLE-NEXT: [[TMP2:%.*]] = zext i16 [[T21]] to i3287; MULTIPLE-NEXT: ret i32 [[TMP2]]88;89; PR-79158-LABEL: @simple3(90; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i1691; PR-79158-NEXT: [[T21:%.*]] = sub i16 [[TMP1]], 192; PR-79158-NEXT: [[TMP2:%.*]] = zext i16 [[T21]] to i3293; PR-79158-NEXT: ret i32 [[TMP2]]94;95 %t1 = uitofp i8 %a to float96 %t2 = fsub float %t1, 1.097 %t3 = fptoui float %t2 to i3298 ret i32 %t399}100 101define i1 @cmp(i8 %a, i8 %b) {102; NONE-LABEL: @cmp(103; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32104; NONE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32105; NONE-NEXT: [[T31:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]106; NONE-NEXT: ret i1 [[T31]]107;108; ONLY64-LABEL: @cmp(109; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i64110; ONLY64-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i64111; ONLY64-NEXT: [[T31:%.*]] = icmp slt i64 [[TMP1]], [[TMP2]]112; ONLY64-NEXT: ret i1 [[T31]]113;114; MULTIPLE-LABEL: @cmp(115; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16116; MULTIPLE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16117; MULTIPLE-NEXT: [[T31:%.*]] = icmp slt i16 [[TMP1]], [[TMP2]]118; MULTIPLE-NEXT: ret i1 [[T31]]119;120; PR-79158-LABEL: @cmp(121; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16122; PR-79158-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16123; PR-79158-NEXT: [[T31:%.*]] = icmp slt i16 [[TMP1]], [[TMP2]]124; PR-79158-NEXT: ret i1 [[T31]]125;126 %t1 = uitofp i8 %a to float127 %t2 = uitofp i8 %b to float128 %t3 = fcmp ult float %t1, %t2129 ret i1 %t3130}131 132define i32 @simple4(i32 %a) {133; CHECK-LABEL: @simple4(134; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64135; CHECK-NEXT: [[T21:%.*]] = add i64 [[TMP1]], 1136; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[T21]] to i32137; CHECK-NEXT: ret i32 [[TMP2]]138;139 %t1 = uitofp i32 %a to double140 %t2 = fadd double %t1, 1.0141 %t3 = fptoui double %t2 to i32142 ret i32 %t3143}144 145define i32 @simple5(i8 %a, i8 %b) {146; NONE-LABEL: @simple5(147; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32148; NONE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32149; NONE-NEXT: [[T31:%.*]] = add i32 [[TMP1]], 1150; NONE-NEXT: [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]151; NONE-NEXT: ret i32 [[T42]]152;153; ONLY64-LABEL: @simple5(154; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i64155; ONLY64-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i64156; ONLY64-NEXT: [[T31:%.*]] = add i64 [[TMP1]], 1157; ONLY64-NEXT: [[T42:%.*]] = mul i64 [[T31]], [[TMP2]]158; ONLY64-NEXT: [[TMP3:%.*]] = trunc i64 [[T42]] to i32159; ONLY64-NEXT: ret i32 [[TMP3]]160;161; MULTIPLE-LABEL: @simple5(162; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32163; MULTIPLE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32164; MULTIPLE-NEXT: [[T31:%.*]] = add i32 [[TMP1]], 1165; MULTIPLE-NEXT: [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]166; MULTIPLE-NEXT: ret i32 [[T42]]167;168; PR-79158-LABEL: @simple5(169; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32170; PR-79158-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32171; PR-79158-NEXT: [[T31:%.*]] = add i32 [[TMP1]], 1172; PR-79158-NEXT: [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]173; PR-79158-NEXT: ret i32 [[T42]]174;175 %t1 = uitofp i8 %a to float176 %t2 = uitofp i8 %b to float177 %t3 = fadd float %t1, 1.0178 %t4 = fmul float %t3, %t2179 %t5 = fptoui float %t4 to i32180 ret i32 %t5181}182 183define i32 @simple6(i8 %a, i8 %b) {184; NONE-LABEL: @simple6(185; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32186; NONE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32187; NONE-NEXT: [[T31:%.*]] = sub i32 0, [[TMP1]]188; NONE-NEXT: [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]189; NONE-NEXT: ret i32 [[T42]]190;191; ONLY64-LABEL: @simple6(192; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i64193; ONLY64-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i64194; ONLY64-NEXT: [[T31:%.*]] = sub i64 0, [[TMP1]]195; ONLY64-NEXT: [[T42:%.*]] = mul i64 [[T31]], [[TMP2]]196; ONLY64-NEXT: [[TMP3:%.*]] = trunc i64 [[T42]] to i32197; ONLY64-NEXT: ret i32 [[TMP3]]198;199; MULTIPLE-LABEL: @simple6(200; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32201; MULTIPLE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32202; MULTIPLE-NEXT: [[T31:%.*]] = sub i32 0, [[TMP1]]203; MULTIPLE-NEXT: [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]204; MULTIPLE-NEXT: ret i32 [[T42]]205;206; PR-79158-LABEL: @simple6(207; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32208; PR-79158-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32209; PR-79158-NEXT: [[T31:%.*]] = sub i32 0, [[TMP1]]210; PR-79158-NEXT: [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]211; PR-79158-NEXT: ret i32 [[T42]]212;213 %t1 = uitofp i8 %a to float214 %t2 = uitofp i8 %b to float215 %t3 = fneg float %t1216 %t4 = fmul float %t3, %t2217 %t5 = fptoui float %t4 to i32218 ret i32 %t5219}220 221; The two chains don't interact - failure of one shouldn't222; cause failure of the other.223 224define i32 @multi1(i8 %a, i8 %b, i8 %c, float %d) {225; NONE-LABEL: @multi1(226; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32227; NONE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32228; NONE-NEXT: [[FC:%.*]] = uitofp i8 [[C:%.*]] to float229; NONE-NEXT: [[X1:%.*]] = add i32 [[TMP1]], [[TMP2]]230; NONE-NEXT: [[Z:%.*]] = fadd float [[FC]], [[D:%.*]]231; NONE-NEXT: [[W:%.*]] = fptoui float [[Z]] to i32232; NONE-NEXT: [[R:%.*]] = add i32 [[X1]], [[W]]233; NONE-NEXT: ret i32 [[R]]234;235; ONLY64-LABEL: @multi1(236; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i64237; ONLY64-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i64238; ONLY64-NEXT: [[FC:%.*]] = uitofp i8 [[C:%.*]] to float239; ONLY64-NEXT: [[X1:%.*]] = add i64 [[TMP1]], [[TMP2]]240; ONLY64-NEXT: [[TMP3:%.*]] = trunc i64 [[X1]] to i32241; ONLY64-NEXT: [[Z:%.*]] = fadd float [[FC]], [[D:%.*]]242; ONLY64-NEXT: [[W:%.*]] = fptoui float [[Z]] to i32243; ONLY64-NEXT: [[R:%.*]] = add i32 [[TMP3]], [[W]]244; ONLY64-NEXT: ret i32 [[R]]245;246; MULTIPLE-LABEL: @multi1(247; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16248; MULTIPLE-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16249; MULTIPLE-NEXT: [[FC:%.*]] = uitofp i8 [[C:%.*]] to float250; MULTIPLE-NEXT: [[X1:%.*]] = add i16 [[TMP1]], [[TMP2]]251; MULTIPLE-NEXT: [[TMP3:%.*]] = zext i16 [[X1]] to i32252; MULTIPLE-NEXT: [[Z:%.*]] = fadd float [[FC]], [[D:%.*]]253; MULTIPLE-NEXT: [[W:%.*]] = fptoui float [[Z]] to i32254; MULTIPLE-NEXT: [[R:%.*]] = add i32 [[TMP3]], [[W]]255; MULTIPLE-NEXT: ret i32 [[R]]256;257; PR-79158-LABEL: @multi1(258; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16259; PR-79158-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16260; PR-79158-NEXT: [[FC:%.*]] = uitofp i8 [[C:%.*]] to float261; PR-79158-NEXT: [[X1:%.*]] = add i16 [[TMP1]], [[TMP2]]262; PR-79158-NEXT: [[TMP3:%.*]] = zext i16 [[X1]] to i32263; PR-79158-NEXT: [[Z:%.*]] = fadd float [[FC]], [[D:%.*]]264; PR-79158-NEXT: [[W:%.*]] = fptoui float [[Z]] to i32265; PR-79158-NEXT: [[R:%.*]] = add i32 [[TMP3]], [[W]]266; PR-79158-NEXT: ret i32 [[R]]267;268 %fa = uitofp i8 %a to float269 %fb = uitofp i8 %b to float270 %fc = uitofp i8 %c to float271 %x = fadd float %fa, %fb272 %y = fptoui float %x to i32273 %z = fadd float %fc, %d274 %w = fptoui float %z to i32275 %r = add i32 %y, %w276 ret i32 %r277}278 279define i16 @simple_negzero(i8 %a) {280; NONE-LABEL: @simple_negzero(281; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32282; NONE-NEXT: [[T21:%.*]] = add i32 [[TMP1]], 0283; NONE-NEXT: [[TMP2:%.*]] = trunc i32 [[T21]] to i16284; NONE-NEXT: ret i16 [[TMP2]]285;286; ONLY64-LABEL: @simple_negzero(287; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i64288; ONLY64-NEXT: [[T21:%.*]] = add i64 [[TMP1]], 0289; ONLY64-NEXT: [[TMP2:%.*]] = trunc i64 [[T21]] to i16290; ONLY64-NEXT: ret i16 [[TMP2]]291;292; MULTIPLE-LABEL: @simple_negzero(293; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16294; MULTIPLE-NEXT: [[T21:%.*]] = add i16 [[TMP1]], 0295; MULTIPLE-NEXT: ret i16 [[T21]]296;297; PR-79158-LABEL: @simple_negzero(298; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16299; PR-79158-NEXT: [[T21:%.*]] = add i16 [[TMP1]], 0300; PR-79158-NEXT: ret i16 [[T21]]301;302 %t1 = uitofp i8 %a to float303 %t2 = fadd fast float %t1, -0.0304 %t3 = fptoui float %t2 to i16305 ret i16 %t3306}307 308define i32 @simple_negative(i8 %call) {309; NONE-LABEL: @simple_negative(310; NONE-NEXT: [[TMP1:%.*]] = sext i8 [[CALL:%.*]] to i32311; NONE-NEXT: [[MUL1:%.*]] = mul i32 [[TMP1]], -3312; NONE-NEXT: [[TMP2:%.*]] = trunc i32 [[MUL1]] to i8313; NONE-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32314; NONE-NEXT: ret i32 [[CONV3]]315;316; ONLY64-LABEL: @simple_negative(317; ONLY64-NEXT: [[TMP1:%.*]] = sext i8 [[CALL:%.*]] to i64318; ONLY64-NEXT: [[MUL1:%.*]] = mul i64 [[TMP1]], -3319; ONLY64-NEXT: [[TMP2:%.*]] = trunc i64 [[MUL1]] to i8320; ONLY64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32321; ONLY64-NEXT: ret i32 [[CONV3]]322;323; MULTIPLE-LABEL: @simple_negative(324; MULTIPLE-NEXT: [[TMP1:%.*]] = sext i8 [[CALL:%.*]] to i16325; MULTIPLE-NEXT: [[MUL1:%.*]] = mul i16 [[TMP1]], -3326; MULTIPLE-NEXT: [[TMP2:%.*]] = trunc i16 [[MUL1]] to i8327; MULTIPLE-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32328; MULTIPLE-NEXT: ret i32 [[CONV3]]329;330; PR-79158-LABEL: @simple_negative(331; PR-79158-NEXT: [[TMP1:%.*]] = sext i8 [[CALL:%.*]] to i16332; PR-79158-NEXT: [[MUL1:%.*]] = mul i16 [[TMP1]], -3333; PR-79158-NEXT: [[TMP2:%.*]] = trunc i16 [[MUL1]] to i8334; PR-79158-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32335; PR-79158-NEXT: ret i32 [[CONV3]]336;337 %conv1 = sitofp i8 %call to float338 %mul = fmul float %conv1, -3.000000e+00339 %conv2 = fptosi float %mul to i8340 %conv3 = sext i8 %conv2 to i32341 ret i32 %conv3342}343 344define i16 @simple_fneg(i8 %a) {345; NONE-LABEL: @simple_fneg(346; NONE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32347; NONE-NEXT: [[T21:%.*]] = sub i32 0, [[TMP1]]348; NONE-NEXT: [[TMP2:%.*]] = trunc i32 [[T21]] to i16349; NONE-NEXT: ret i16 [[TMP2]]350;351; ONLY64-LABEL: @simple_fneg(352; ONLY64-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i64353; ONLY64-NEXT: [[T21:%.*]] = sub i64 0, [[TMP1]]354; ONLY64-NEXT: [[TMP2:%.*]] = trunc i64 [[T21]] to i16355; ONLY64-NEXT: ret i16 [[TMP2]]356;357; MULTIPLE-LABEL: @simple_fneg(358; MULTIPLE-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16359; MULTIPLE-NEXT: [[T21:%.*]] = sub i16 0, [[TMP1]]360; MULTIPLE-NEXT: ret i16 [[T21]]361;362; PR-79158-LABEL: @simple_fneg(363; PR-79158-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16364; PR-79158-NEXT: [[T21:%.*]] = sub i16 0, [[TMP1]]365; PR-79158-NEXT: ret i16 [[T21]]366;367 %t1 = uitofp i8 %a to float368 %t2 = fneg fast float %t1369 %t3 = fptoui float %t2 to i16370 ret i16 %t3371}372 373;374; Negative tests375;376 377; The two chains intersect, which means because one fails, no378; transform can occur.379 380define i32 @neg_multi1(i8 %a, i8 %b, i8 %c, float %d) {381; CHECK-LABEL: @neg_multi1(382; CHECK-NEXT: [[FA:%.*]] = uitofp i8 [[A:%.*]] to float383; CHECK-NEXT: [[FC:%.*]] = uitofp i8 [[C:%.*]] to float384; CHECK-NEXT: [[X:%.*]] = fadd float [[FA]], [[FC]]385; CHECK-NEXT: [[Y:%.*]] = fptoui float [[X]] to i32386; CHECK-NEXT: [[Z:%.*]] = fadd float [[FC]], [[D:%.*]]387; CHECK-NEXT: [[W:%.*]] = fptoui float [[Z]] to i32388; CHECK-NEXT: [[R:%.*]] = add i32 [[Y]], [[W]]389; CHECK-NEXT: ret i32 [[R]]390;391 %fa = uitofp i8 %a to float392 %fc = uitofp i8 %c to float393 %x = fadd float %fa, %fc394 %y = fptoui float %x to i32395 %z = fadd float %fc, %d396 %w = fptoui float %z to i32397 %r = add i32 %y, %w398 ret i32 %r399}400 401; The i32 * i32 = i64, which has 64 bits, which is greater than the 52 bits402; that can be exactly represented in a double.403 404define i64 @neg_muld(i32 %a, i32 %b) {405; CHECK-LABEL: @neg_muld(406; CHECK-NEXT: [[FA:%.*]] = uitofp i32 [[A:%.*]] to double407; CHECK-NEXT: [[FB:%.*]] = uitofp i32 [[B:%.*]] to double408; CHECK-NEXT: [[MUL:%.*]] = fmul double [[FA]], [[FB]]409; CHECK-NEXT: [[R:%.*]] = fptoui double [[MUL]] to i64410; CHECK-NEXT: ret i64 [[R]]411;412 %fa = uitofp i32 %a to double413 %fb = uitofp i32 %b to double414 %mul = fmul double %fa, %fb415 %r = fptoui double %mul to i64416 ret i64 %r417}418 419; The i16 * i16 = i32, which can't be represented in a float, but can in a420; double. This should fail, as the written code uses floats, not doubles so421; the original result may be inaccurate.422 423define i32 @neg_mulf(i16 %a, i16 %b) {424; CHECK-LABEL: @neg_mulf(425; CHECK-NEXT: [[FA:%.*]] = uitofp i16 [[A:%.*]] to float426; CHECK-NEXT: [[FB:%.*]] = uitofp i16 [[B:%.*]] to float427; CHECK-NEXT: [[MUL:%.*]] = fmul float [[FA]], [[FB]]428; CHECK-NEXT: [[R:%.*]] = fptoui float [[MUL]] to i32429; CHECK-NEXT: ret i32 [[R]]430;431 %fa = uitofp i16 %a to float432 %fb = uitofp i16 %b to float433 %mul = fmul float %fa, %fb434 %r = fptoui float %mul to i32435 ret i32 %r436}437 438; "false" doesn't have an icmp equivalent.439 440define i1 @neg_cmp(i8 %a, i8 %b) {441; CHECK-LABEL: @neg_cmp(442; CHECK-NEXT: [[T1:%.*]] = uitofp i8 [[A:%.*]] to float443; CHECK-NEXT: [[T2:%.*]] = uitofp i8 [[B:%.*]] to float444; CHECK-NEXT: [[T3:%.*]] = fcmp false float [[T1]], [[T2]]445; CHECK-NEXT: ret i1 [[T3]]446;447 %t1 = uitofp i8 %a to float448 %t2 = uitofp i8 %b to float449 %t3 = fcmp false float %t1, %t2450 ret i1 %t3451}452 453; Division isn't a supported operator.454 455define i16 @neg_div(i8 %a) {456; CHECK-LABEL: @neg_div(457; CHECK-NEXT: [[T1:%.*]] = uitofp i8 [[A:%.*]] to float458; CHECK-NEXT: [[T2:%.*]] = fdiv float [[T1]], 1.000000e+00459; CHECK-NEXT: [[T3:%.*]] = fptoui float [[T2]] to i16460; CHECK-NEXT: ret i16 [[T3]]461;462 %t1 = uitofp i8 %a to float463 %t2 = fdiv float %t1, 1.0464 %t3 = fptoui float %t2 to i16465 ret i16 %t3466}467 468; 1.2 is not an integer.469 470define i16 @neg_remainder(i8 %a) {471; CHECK-LABEL: @neg_remainder(472; CHECK-NEXT: [[T1:%.*]] = uitofp i8 [[A:%.*]] to float473; CHECK-NEXT: [[T2:%.*]] = fadd float [[T1]], 1.250000e+00474; CHECK-NEXT: [[T3:%.*]] = fptoui float [[T2]] to i16475; CHECK-NEXT: ret i16 [[T3]]476;477 %t1 = uitofp i8 %a to float478 %t2 = fadd float %t1, 1.25479 %t3 = fptoui float %t2 to i16480 ret i16 %t3481}482 483; i80 > i64, which is the largest bitwidth handleable by default.484 485define i80 @neg_toolarge(i80 %a) {486; CHECK-LABEL: @neg_toolarge(487; CHECK-NEXT: [[T1:%.*]] = uitofp i80 [[A:%.*]] to fp128488; CHECK-NEXT: [[T2:%.*]] = fadd fp128 [[T1]], [[T1]]489; CHECK-NEXT: [[T3:%.*]] = fptoui fp128 [[T2]] to i80490; CHECK-NEXT: ret i80 [[T3]]491;492 %t1 = uitofp i80 %a to fp128493 %t2 = fadd fp128 %t1, %t1494 %t3 = fptoui fp128 %t2 to i80495 ret i80 %t3496}497 498; The sequence %t1..%t3 cannot be converted because %t4 uses %t2.499 500define i32 @neg_calluser(i32 %value) {501; CHECK-LABEL: @neg_calluser(502; CHECK-NEXT: [[T1:%.*]] = sitofp i32 [[VALUE:%.*]] to double503; CHECK-NEXT: [[T2:%.*]] = fadd double [[T1]], 1.000000e+00504; CHECK-NEXT: [[T3:%.*]] = fcmp olt double [[T2]], 0.000000e+00505; CHECK-NEXT: [[T4:%.*]] = tail call double @g(double [[T2]])506; CHECK-NEXT: [[T5:%.*]] = fptosi double [[T4]] to i32507; CHECK-NEXT: [[T6:%.*]] = zext i1 [[T3]] to i32508; CHECK-NEXT: [[T7:%.*]] = add i32 [[T6]], [[T5]]509; CHECK-NEXT: ret i32 [[T7]]510;511 %t1 = sitofp i32 %value to double512 %t2 = fadd double %t1, 1.0513 %t3 = fcmp olt double %t2, 0.000000e+00514 %t4 = tail call double @g(double %t2)515 %t5 = fptosi double %t4 to i32516 %t6 = zext i1 %t3 to i32517 %t7 = add i32 %t6, %t5518 ret i32 %t7519}520 521declare double @g(double)522 523define <4 x i16> @neg_vector(<4 x i8> %a) {524; CHECK-LABEL: @neg_vector(525; CHECK-NEXT: [[T1:%.*]] = uitofp <4 x i8> [[A:%.*]] to <4 x float>526; CHECK-NEXT: [[T2:%.*]] = fptoui <4 x float> [[T1]] to <4 x i16>527; CHECK-NEXT: ret <4 x i16> [[T2]]528;529 %t1 = uitofp <4 x i8> %a to <4 x float>530 %t2 = fptoui <4 x float> %t1 to <4 x i16>531 ret <4 x i16> %t2532}533 534; Don't crash while processing unreachable (non-standard) IR.535 536define void @PR38502() {537; CHECK-LABEL: @PR38502(538; CHECK-NEXT: entry:539; CHECK-NEXT: ret void540; CHECK: bogusBB:541; CHECK-NEXT: [[INC1:%.*]] = fadd double [[INC:%.*]], 1.000000e+00542; CHECK-NEXT: [[INC]] = fadd double [[INC1]], 1.000000e+00543; CHECK-NEXT: [[TOBOOL:%.*]] = fcmp une double [[INC]], 0.000000e+00544; CHECK-NEXT: br label [[BOGUSBB:%.*]]545;546entry:547 ret void548 549bogusBB: ; preds = %bogusBB550 %inc1 = fadd double %inc, 1.000000e+00551 %inc = fadd double %inc1, 1.000000e+00552 %tobool = fcmp une double %inc, 0.000000e+00553 br label %bogusBB554}555