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1; RUN: opt -O3 -S < %s | FileCheck %s2; Show 'optnone' suppresses optimizations.3 4; Two attribute groups that differ only by 'optnone'.5; 'optnone' requires 'noinline' so #0 is 'noinline' by itself,6; even though it would otherwise be irrelevant to this example.7attributes #0 = { noinline }8attributes #1 = { noinline optnone }9 10; int iadd(int a, int b){ return a + b; }11 12define i32 @iadd_optimize(i32 %a, i32 %b) #0 {13entry:14 %a.addr = alloca i32, align 415 %b.addr = alloca i32, align 416 store i32 %a, ptr %a.addr, align 417 store i32 %b, ptr %b.addr, align 418 %0 = load i32, ptr %a.addr, align 419 %1 = load i32, ptr %b.addr, align 420 %add = add nsw i32 %0, %121 ret i32 %add22}23 24; CHECK-LABEL: @iadd_optimize25; CHECK-NOT: alloca26; CHECK-NOT: store27; CHECK-NOT: load28; CHECK: ret29 30define i32 @iadd_optnone(i32 %a, i32 %b) #1 {31entry:32 %a.addr = alloca i32, align 433 %b.addr = alloca i32, align 434 store i32 %a, ptr %a.addr, align 435 store i32 %b, ptr %b.addr, align 436 %0 = load i32, ptr %a.addr, align 437 %1 = load i32, ptr %b.addr, align 438 %add = add nsw i32 %0, %139 ret i32 %add40}41 42; CHECK-LABEL: @iadd_optnone43; CHECK: alloca i3244; CHECK: alloca i3245; CHECK: store i3246; CHECK: store i3247; CHECK: load i3248; CHECK: load i3249; CHECK: add nsw i3250; CHECK: ret i3251 52; float fsub(float a, float b){ return a - b; }53 54define float @fsub_optimize(float %a, float %b) #0 {55entry:56 %a.addr = alloca float, align 457 %b.addr = alloca float, align 458 store float %a, ptr %a.addr, align 459 store float %b, ptr %b.addr, align 460 %0 = load float, ptr %a.addr, align 461 %1 = load float, ptr %b.addr, align 462 %sub = fsub float %0, %163 ret float %sub64}65 66; CHECK-LABEL: @fsub_optimize67; CHECK-NOT: alloca68; CHECK-NOT: store69; CHECK-NOT: load70; CHECK: ret71 72define float @fsub_optnone(float %a, float %b) #1 {73entry:74 %a.addr = alloca float, align 475 %b.addr = alloca float, align 476 store float %a, ptr %a.addr, align 477 store float %b, ptr %b.addr, align 478 %0 = load float, ptr %a.addr, align 479 %1 = load float, ptr %b.addr, align 480 %sub = fsub float %0, %181 ret float %sub82}83 84; CHECK-LABEL: @fsub_optnone85; CHECK: alloca float86; CHECK: alloca float87; CHECK: store float88; CHECK: store float89; CHECK: load float90; CHECK: load float91; CHECK: fsub float92; CHECK: ret float93 94; typedef float __attribute__((ext_vector_type(4))) float4;95; float4 vmul(float4 a, float4 b){ return a * b; }96 97define <4 x float> @vmul_optimize(<4 x float> %a, <4 x float> %b) #0 {98entry:99 %a.addr = alloca <4 x float>, align 16100 %b.addr = alloca <4 x float>, align 16101 store <4 x float> %a, ptr %a.addr, align 16102 store <4 x float> %b, ptr %b.addr, align 16103 %0 = load <4 x float>, ptr %a.addr, align 16104 %1 = load <4 x float>, ptr %b.addr, align 16105 %mul = fmul <4 x float> %0, %1106 ret <4 x float> %mul107}108 109; CHECK-LABEL: @vmul_optimize110; CHECK-NOT: alloca111; CHECK-NOT: store112; CHECK-NOT: load113; CHECK: ret114 115define <4 x float> @vmul_optnone(<4 x float> %a, <4 x float> %b) #1 {116entry:117 %a.addr = alloca <4 x float>, align 16118 %b.addr = alloca <4 x float>, align 16119 store <4 x float> %a, ptr %a.addr, align 16120 store <4 x float> %b, ptr %b.addr, align 16121 %0 = load <4 x float>, ptr %a.addr, align 16122 %1 = load <4 x float>, ptr %b.addr, align 16123 %mul = fmul <4 x float> %0, %1124 ret <4 x float> %mul125}126 127; CHECK-LABEL: @vmul_optnone128; CHECK: alloca <4 x float>129; CHECK: alloca <4 x float>130; CHECK: store <4 x float>131; CHECK: store <4 x float>132; CHECK: load <4 x float>133; CHECK: load <4 x float>134; CHECK: fmul <4 x float>135; CHECK: ret136