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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=gvn -enable-load-pre < %s | FileCheck %s --check-prefixes=CHECK,MDEP3; RUN: opt -S -passes='gvn<memoryssa>' -enable-load-pre < %s | FileCheck %s --check-prefixes=CHECK,MSSA4;5; Make sure the load in bb3.backedge is removed and moved into bb1 after the6; call. This makes the non-call case faster.7;8; This test is derived from this C++ code (GCC PR 37810):9; void g();10; struct A {11; int n; int m;12; A& operator++(void) { ++n; if (n == m) g(); return *this; }13; A() : n(0), m(0) { }14; friend bool operator!=(A const& a1, A const& a2) { return a1.n != a2.n; }15; };16; void testfunction(A& iter) { A const end; while (iter != end) ++iter; }17;18target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"19 %struct.A = type { i32, i32 }20 21define void @_Z12testfunctionR1A(ptr %iter) {22; MDEP-LABEL: @_Z12testfunctionR1A(23; MDEP-NEXT: entry:24; MDEP-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 425; MDEP-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 026; MDEP-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]]27; MDEP: bb.nph:28; MDEP-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 129; MDEP-NEXT: br label [[BB:%.*]]30; MDEP: bb:31; MDEP-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ]32; MDEP-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 133; MDEP-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 434; MDEP-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 435; MDEP-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]]36; MDEP-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]]37; MDEP: bb1:38; MDEP-NEXT: tail call void @_Z1gv()39; MDEP-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ITER]], align 440; MDEP-NEXT: br label [[BB3_BACKEDGE]]41; MDEP: bb3.backedge:42; MDEP-NEXT: [[TMP6]] = phi i32 [ [[DOTPRE]], [[BB1]] ], [ [[TMP3]], [[BB]] ]43; MDEP-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 044; MDEP-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]]45; MDEP: return:46; MDEP-NEXT: ret void47;48; MSSA-LABEL: @_Z12testfunctionR1A(49; MSSA-NEXT: entry:50; MSSA-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 451; MSSA-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 052; MSSA-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]]53; MSSA: bb.nph:54; MSSA-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 155; MSSA-NEXT: br label [[BB:%.*]]56; MSSA: bb:57; MSSA-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ]58; MSSA-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 159; MSSA-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 460; MSSA-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 461; MSSA-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]]62; MSSA-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]]63; MSSA: bb1:64; MSSA-NEXT: tail call void @_Z1gv()65; MSSA-NEXT: br label [[BB3_BACKEDGE]]66; MSSA: bb3.backedge:67; MSSA-NEXT: [[TMP6]] = load i32, ptr [[ITER]], align 468; MSSA-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 069; MSSA-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]]70; MSSA: return:71; MSSA-NEXT: ret void72;73entry:74 %0 = getelementptr %struct.A, ptr %iter, i32 0, i32 0 ; <ptr> [#uses=3]75 %1 = load i32, ptr %0, align 4 ; <i32> [#uses=2]76 %2 = icmp eq i32 %1, 0 ; <i1> [#uses=1]77 br i1 %2, label %return, label %bb.nph78 79bb.nph: ; preds = %entry80 %3 = getelementptr %struct.A, ptr %iter, i32 0, i32 1 ; <ptr> [#uses=1]81 br label %bb82 83bb: ; preds = %bb3.backedge, %bb.nph84 %.rle = phi i32 [ %1, %bb.nph ], [ %7, %bb3.backedge ] ; <i32> [#uses=1]85 %4 = add i32 %.rle, 1 ; <i32> [#uses=2]86 store i32 %4, ptr %0, align 487 %5 = load i32, ptr %3, align 4 ; <i32> [#uses=1]88 %6 = icmp eq i32 %4, %5 ; <i1> [#uses=1]89 br i1 %6, label %bb1, label %bb3.backedge90 91bb1: ; preds = %bb92 tail call void @_Z1gv()93 br label %bb3.backedge94 95bb3.backedge: ; preds = %bb, %bb196 %7 = load i32, ptr %0, align 4 ; <i32> [#uses=2]97 %8 = icmp eq i32 %7, 0 ; <i1> [#uses=1]98 br i1 %8, label %return, label %bb99 100return: ; preds = %bb3.backedge, %entry101 ret void102}103 104declare void @_Z1gv()105;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:106; CHECK: {{.*}}107