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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=gvn -S | FileCheck %s --check-prefixes=CHECK,MDEP3; RUN: opt < %s -passes='gvn<memoryssa>' -S | FileCheck %s --check-prefixes=CHECK,MSSA4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"5 6@a = common global [100 x i64] zeroinitializer, align 167@b = common global [100 x i64] zeroinitializer, align 168@g1 = common global i64 0, align 89@g2 = common global i64 0, align 810@g3 = common global i64 0, align 811declare i64 @goo(...) local_unnamed_addr #112 13define void @test1(i64 %a, i64 %b, i64 %c, i64 %d) {14; CHECK-LABEL: @test1(15; CHECK-NEXT: entry:16; CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[B:%.*]], [[A:%.*]]17; CHECK-NEXT: store i64 [[MUL]], ptr @g1, align 818; CHECK-NEXT: [[T0:%.*]] = load i64, ptr @g2, align 819; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[T0]], 320; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]21; CHECK: if.then:22; CHECK-NEXT: [[MUL2:%.*]] = mul nsw i64 [[D:%.*]], [[C:%.*]]23; CHECK-NEXT: store i64 [[MUL2]], ptr @g2, align 824; CHECK-NEXT: br label [[IF_END]]25; CHECK: if.end:26; CHECK-NEXT: [[MUL3_PRE_PHI:%.*]] = phi i64 [ [[MUL2]], [[IF_THEN]] ], [ [[MUL]], [[ENTRY:%.*]] ]27; CHECK-NEXT: [[B_ADDR_0:%.*]] = phi i64 [ [[D]], [[IF_THEN]] ], [ [[B]], [[ENTRY]] ]28; CHECK-NEXT: [[A_ADDR_0:%.*]] = phi i64 [ [[C]], [[IF_THEN]] ], [ [[A]], [[ENTRY]] ]29; CHECK-NEXT: store i64 [[MUL3_PRE_PHI]], ptr @g3, align 830; CHECK-NEXT: ret void31;32entry:33 %mul = mul nsw i64 %b, %a34 store i64 %mul, ptr @g1, align 835 %t0 = load i64, ptr @g2, align 836 %cmp = icmp sgt i64 %t0, 337 br i1 %cmp, label %if.then, label %if.end38 39if.then: ; preds = %entry40 %mul2 = mul nsw i64 %d, %c41 store i64 %mul2, ptr @g2, align 842 br label %if.end43 44; Check phi-translate works and mul is removed.45if.end: ; preds = %if.then, %entry46 %b.addr.0 = phi i64 [ %d, %if.then ], [ %b, %entry ]47 %a.addr.0 = phi i64 [ %c, %if.then ], [ %a, %entry ]48 %mul3 = mul nsw i64 %a.addr.0, %b.addr.049 store i64 %mul3, ptr @g3, align 850 ret void51}52 53define void @test2(i64 %i) {54; MDEP-LABEL: @test2(55; MDEP-NEXT: entry:56; MDEP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i64], ptr @a, i64 0, i64 [[I:%.*]]57; MDEP-NEXT: [[T0:%.*]] = load i64, ptr [[ARRAYIDX]], align 858; MDEP-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [100 x i64], ptr @b, i64 0, i64 [[I]]59; MDEP-NEXT: [[T1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 860; MDEP-NEXT: [[MUL:%.*]] = mul nsw i64 [[T1]], [[T0]]61; MDEP-NEXT: store i64 [[MUL]], ptr @g1, align 862; MDEP-NEXT: [[CMP:%.*]] = icmp sgt i64 [[MUL]], 363; MDEP-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]64; MDEP: if.then:65; MDEP-NEXT: [[CALL:%.*]] = tail call i64 (...) @goo()66; MDEP-NEXT: store i64 [[CALL]], ptr @g2, align 867; MDEP-NEXT: [[T2_PRE:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @a, i64 24), align 868; MDEP-NEXT: [[T3_PRE:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @b, i64 24), align 869; MDEP-NEXT: [[DOTPRE:%.*]] = mul nsw i64 [[T3_PRE]], [[T2_PRE]]70; MDEP-NEXT: br label [[IF_END]]71; MDEP: if.end:72; MDEP-NEXT: [[MUL5_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE]], [[IF_THEN]] ], [ [[MUL]], [[ENTRY:%.*]] ]73; MDEP-NEXT: [[T3:%.*]] = phi i64 [ [[T3_PRE]], [[IF_THEN]] ], [ [[T1]], [[ENTRY]] ]74; MDEP-NEXT: [[T2:%.*]] = phi i64 [ [[T2_PRE]], [[IF_THEN]] ], [ [[T0]], [[ENTRY]] ]75; MDEP-NEXT: [[I_ADDR_0:%.*]] = phi i64 [ 3, [[IF_THEN]] ], [ [[I]], [[ENTRY]] ]76; MDEP-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [100 x i64], ptr @a, i64 0, i64 [[I_ADDR_0]]77; MDEP-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [100 x i64], ptr @b, i64 0, i64 [[I_ADDR_0]]78; MDEP-NEXT: store i64 [[MUL5_PRE_PHI]], ptr @g3, align 879; MDEP-NEXT: ret void80;81; MSSA-LABEL: @test2(82; MSSA-NEXT: entry:83; MSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i64], ptr @a, i64 0, i64 [[I:%.*]]84; MSSA-NEXT: [[T0:%.*]] = load i64, ptr [[ARRAYIDX]], align 885; MSSA-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [100 x i64], ptr @b, i64 0, i64 [[I]]86; MSSA-NEXT: [[T1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 887; MSSA-NEXT: [[MUL:%.*]] = mul nsw i64 [[T1]], [[T0]]88; MSSA-NEXT: store i64 [[MUL]], ptr @g1, align 889; MSSA-NEXT: [[CMP:%.*]] = icmp sgt i64 [[MUL]], 390; MSSA-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]91; MSSA: if.then:92; MSSA-NEXT: [[CALL:%.*]] = tail call i64 (...) @goo()93; MSSA-NEXT: store i64 [[CALL]], ptr @g2, align 894; MSSA-NEXT: br label [[IF_END]]95; MSSA: if.end:96; MSSA-NEXT: [[I_ADDR_0:%.*]] = phi i64 [ 3, [[IF_THEN]] ], [ [[I]], [[ENTRY:%.*]] ]97; MSSA-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [100 x i64], ptr @a, i64 0, i64 [[I_ADDR_0]]98; MSSA-NEXT: [[T2:%.*]] = load i64, ptr [[ARRAYIDX3]], align 899; MSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [100 x i64], ptr @b, i64 0, i64 [[I_ADDR_0]]100; MSSA-NEXT: [[T3:%.*]] = load i64, ptr [[ARRAYIDX4]], align 8101; MSSA-NEXT: [[MUL5:%.*]] = mul nsw i64 [[T3]], [[T2]]102; MSSA-NEXT: store i64 [[MUL5]], ptr @g3, align 8103; MSSA-NEXT: ret void104;105entry:106 %arrayidx = getelementptr inbounds [100 x i64], ptr @a, i64 0, i64 %i107 %t0 = load i64, ptr %arrayidx, align 8108 %arrayidx1 = getelementptr inbounds [100 x i64], ptr @b, i64 0, i64 %i109 %t1 = load i64, ptr %arrayidx1, align 8110 %mul = mul nsw i64 %t1, %t0111 store i64 %mul, ptr @g1, align 8112 %cmp = icmp sgt i64 %mul, 3113 br i1 %cmp, label %if.then, label %if.end114 115; Check phi-translate works for the phi generated by loadpre. A new mul will be116; inserted in if.then block.117if.then: ; preds = %entry118 %call = tail call i64 (...) @goo() #2119 store i64 %call, ptr @g2, align 8120 br label %if.end121 122if.end: ; preds = %if.then, %entry123 %i.addr.0 = phi i64 [ 3, %if.then ], [ %i, %entry ]124 %arrayidx3 = getelementptr inbounds [100 x i64], ptr @a, i64 0, i64 %i.addr.0125 %t2 = load i64, ptr %arrayidx3, align 8126 %arrayidx4 = getelementptr inbounds [100 x i64], ptr @b, i64 0, i64 %i.addr.0127 %t3 = load i64, ptr %arrayidx4, align 8128 %mul5 = mul nsw i64 %t3, %t2129 store i64 %mul5, ptr @g3, align 8130 ret void131}132 133; Check phi-translate doesn't go through backedge, which may lead to incorrect134; pre transformation.135define void @test3(i64 %N, ptr nocapture readonly %a) {136; CHECK-LABEL: @test3(137; CHECK-NEXT: entry:138; CHECK-NEXT: br label [[FOR_COND:%.*]]139; CHECK: for.cond:140; CHECK-NEXT: [[I_0:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY:%.*]] ]141; CHECK-NEXT: [[ADD]] = add nuw nsw i64 [[I_0]], 1142; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[ADD]]143; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8144; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[I_0]], [[N:%.*]]145; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]146; CHECK: for.body:147; CHECK-NEXT: [[CALL:%.*]] = tail call i64 (...) @goo()148; CHECK-NEXT: [[ADD1:%.*]] = sub nsw i64 0, [[CALL]]149; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[TMP0]], [[ADD1]]150; CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_COND]], label [[FOR_END]]151; CHECK: for.end:152; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[I_0]]153; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8154; CHECK-NEXT: store i64 [[TMP1]], ptr @g1, align 8155; CHECK-NEXT: ret void156;157entry:158 br label %for.cond159 160for.cond: ; preds = %for.body, %entry161 %i.0 = phi i64 [ 0, %entry ], [ %add, %for.body ]162 %add = add nuw nsw i64 %i.0, 1163 %arrayidx = getelementptr inbounds i64, ptr %a, i64 %add164 %tmp0 = load i64, ptr %arrayidx, align 8165 %cmp = icmp slt i64 %i.0, %N166 br i1 %cmp, label %for.body, label %for.end167 168for.body: ; preds = %for.cond169 %call = tail call i64 (...) @goo() #2170 %add1 = sub nsw i64 0, %call171 %tobool = icmp eq i64 %tmp0, %add1172 br i1 %tobool, label %for.cond, label %for.end173 174for.end: ; preds = %for.body, %for.cond175 %i.0.lcssa = phi i64 [ %i.0, %for.body ], [ %i.0, %for.cond ]176 %arrayidx2 = getelementptr inbounds i64, ptr %a, i64 %i.0.lcssa177 %tmp1 = load i64, ptr %arrayidx2, align 8178 store i64 %tmp1, ptr @g1, align 8179 ret void180}181 182; It is incorrect to use the value of %andres in last loop iteration183; to do pre.184define i32 @test4(i32 %cond, i32 %SectionAttrs.0231.ph, ptr %AttrFlag) {185; CHECK-LABEL: @test4(186; CHECK-NEXT: for.body.preheader:187; CHECK-NEXT: [[T514:%.*]] = load volatile i32, ptr [[ATTRFLAG:%.*]], align 4188; CHECK-NEXT: br label [[FOR_BODY:%.*]]189; CHECK: for.body:190; CHECK-NEXT: [[T320:%.*]] = phi i32 [ [[T334:%.*]], [[BB343:%.*]] ], [ [[T514]], [[FOR_BODY_PREHEADER:%.*]] ]191; CHECK-NEXT: [[ANDRES:%.*]] = and i32 [[T320]], [[SECTIONATTRS_0231_PH:%.*]]192; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i32 [[ANDRES]], 0193; CHECK-NEXT: br i1 [[TOBOOL1]], label [[BB343]], label [[CRITEDGE_LOOPEXIT:%.*]]194; CHECK: bb343:195; CHECK-NEXT: [[T334]] = load volatile i32, ptr [[ATTRFLAG]], align 4196; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i32 [[COND:%.*]], 0197; CHECK-NEXT: br i1 [[TOBOOL2]], label [[CRITEDGE_LOOPEXIT]], label [[FOR_BODY]]198; CHECK: critedge.loopexit:199; CHECK-NEXT: unreachable200;201for.body.preheader:202 %t514 = load volatile i32, ptr %AttrFlag203 br label %for.body204 205for.body:206 %t320 = phi i32 [ %t334, %bb343 ], [ %t514, %for.body.preheader ]207 %andres = and i32 %t320, %SectionAttrs.0231.ph208 %tobool1 = icmp eq i32 %andres, 0209 br i1 %tobool1, label %bb343, label %critedge.loopexit210 211bb343:212 %t334 = load volatile i32, ptr %AttrFlag213 %tobool2 = icmp eq i32 %cond, 0214 br i1 %tobool2, label %critedge.loopexit, label %for.body215 216critedge.loopexit:217 unreachable218}219 220declare void @bar(...) local_unnamed_addr #1221 222; Check sub expression will be pre transformed.223define i64 @test5(ptr %start, ptr %e, i32 %n1, i32 %n2) local_unnamed_addr #0 {224; CHECK-LABEL: @test5(225; CHECK-NEXT: entry:226; CHECK-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[E:%.*]] to i64227; CHECK-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[START:%.*]] to i64228; CHECK-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]229; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[SUB_PTR_SUB]], 4000230; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END3:%.*]]231; CHECK: if.then:232; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[N1:%.*]], [[N2:%.*]]233; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_ELSE:%.*]]234; CHECK: if.then2:235; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[START]], i64 800236; CHECK-NEXT: [[DOTPRE:%.*]] = ptrtoint ptr [[ADD_PTR]] to i64237; CHECK-NEXT: [[DOTPRE1:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[DOTPRE]]238; CHECK-NEXT: br label [[IF_END3]]239; CHECK: if.else:240; CHECK-NEXT: tail call void (...) @bar()241; CHECK-NEXT: br label [[IF_END3]]242; CHECK: if.end3:243; CHECK-NEXT: [[SUB_PTR_SUB6_PRE_PHI:%.*]] = phi i64 [ [[SUB_PTR_SUB]], [[IF_ELSE]] ], [ [[DOTPRE1]], [[IF_THEN2]] ], [ [[SUB_PTR_SUB]], [[ENTRY:%.*]] ]244; CHECK-NEXT: [[SUB_PTR_RHS_CAST5_PRE_PHI:%.*]] = phi i64 [ [[SUB_PTR_RHS_CAST]], [[IF_ELSE]] ], [ [[DOTPRE]], [[IF_THEN2]] ], [ [[SUB_PTR_RHS_CAST]], [[ENTRY]] ]245; CHECK-NEXT: [[P_0:%.*]] = phi ptr [ [[ADD_PTR]], [[IF_THEN2]] ], [ [[START]], [[IF_ELSE]] ], [ [[START]], [[ENTRY]] ]246; CHECK-NEXT: [[SUB_PTR_DIV7:%.*]] = ashr exact i64 [[SUB_PTR_SUB6_PRE_PHI]], 2247; CHECK-NEXT: ret i64 [[SUB_PTR_DIV7]]248;249entry:250 %sub.ptr.lhs.cast = ptrtoint ptr %e to i64251 %sub.ptr.rhs.cast = ptrtoint ptr %start to i64252 %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast253 %cmp = icmp sgt i64 %sub.ptr.sub, 4000254 br i1 %cmp, label %if.then, label %if.end3255 256if.then: ; preds = %entry257 %cmp1 = icmp sgt i32 %n1, %n2258 br i1 %cmp1, label %if.then2, label %if.else259 260if.then2: ; preds = %if.then261 %add.ptr = getelementptr inbounds i32, ptr %start, i64 800262 br label %if.end3263 264if.else: ; preds = %if.then265 tail call void (...) @bar() #2266 br label %if.end3267 268if.end3: ; preds = %if.then2, %if.else, %entry269 %p.0 = phi ptr [ %add.ptr, %if.then2 ], [ %start, %if.else ], [ %start, %entry ]270 %sub.ptr.rhs.cast5 = ptrtoint ptr %p.0 to i64271 %sub.ptr.sub6 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast5272 %sub.ptr.div7 = ashr exact i64 %sub.ptr.sub6, 2273 ret i64 %sub.ptr.div7274}275 276; Here the load from arrayidx1 is partially redundant, but its value is277; available in if.then. Check that we correctly phi-translate to the phi that278; the load has been replaced with.279define void @test6(ptr %ptr, i1 %arg) {280; MDEP-LABEL: @test6(281; MDEP-NEXT: entry:282; MDEP-NEXT: [[ARRAYIDX1_PHI_TRANS_INSERT:%.*]] = getelementptr inbounds i32, ptr [[PTR:%.*]], i64 1283; MDEP-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ARRAYIDX1_PHI_TRANS_INSERT]], align 4284; MDEP-NEXT: br label [[WHILE:%.*]]285; MDEP: while:286; MDEP-NEXT: [[TMP0:%.*]] = phi i32 [ [[DOTPRE]], [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[IF_END:%.*]] ]287; MDEP-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY]] ], [ [[I_NEXT:%.*]], [[IF_END]] ]288; MDEP-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i64 [[I]]289; MDEP-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1290; MDEP-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i64 [[I_NEXT]]291; MDEP-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4292; MDEP-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]]293; MDEP-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END]]294; MDEP: if.then:295; MDEP-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX1]], align 4296; MDEP-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX2]], align 4297; MDEP-NEXT: br label [[IF_END]]298; MDEP: if.end:299; MDEP-NEXT: [[TMP2]] = phi i32 [ [[TMP0]], [[IF_THEN]] ], [ [[TMP1]], [[WHILE]] ]300; MDEP-NEXT: br i1 [[ARG:%.*]], label [[WHILE_END:%.*]], label [[WHILE]]301; MDEP: while.end:302; MDEP-NEXT: ret void303;304; MSSA-LABEL: @test6(305; MSSA-NEXT: entry:306; MSSA-NEXT: br label [[WHILE:%.*]]307; MSSA: while:308; MSSA-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ]309; MSSA-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[PTR:%.*]], i64 [[I]]310; MSSA-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4311; MSSA-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1312; MSSA-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i64 [[I_NEXT]]313; MSSA-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4314; MSSA-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]]315; MSSA-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END]]316; MSSA: if.then:317; MSSA-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX1]], align 4318; MSSA-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX2]], align 4319; MSSA-NEXT: br label [[IF_END]]320; MSSA: if.end:321; MSSA-NEXT: br i1 [[ARG:%.*]], label [[WHILE_END:%.*]], label [[WHILE]]322; MSSA: while.end:323; MSSA-NEXT: ret void324;325entry:326 br label %while327 328while:329 %i = phi i64 [ 1, %entry ], [ %i.next, %if.end ]330 %arrayidx1 = getelementptr inbounds i32, ptr %ptr, i64 %i331 %0 = load i32, ptr %arrayidx1, align 4332 %i.next = add nuw nsw i64 %i, 1333 %arrayidx2 = getelementptr inbounds i32, ptr %ptr, i64 %i.next334 %1 = load i32, ptr %arrayidx2, align 4335 %cmp = icmp sgt i32 %0, %1336 br i1 %cmp, label %if.then, label %if.end337 338if.then:339 store i32 %1, ptr %arrayidx1, align 4340 store i32 %0, ptr %arrayidx2, align 4341 br label %if.end342 343if.end:344 br i1 %arg, label %while.end, label %while345 346while.end:347 ret void348}349 350; Load from arrayidx2 is partially redundant, check that address translation can351; fold sext + trunc across phi node together.352define i32 @test7(ptr noalias %ptr1, ptr noalias %ptr2, i32 %i, i1 %cond) {353; MDEP-LABEL: @test7(354; MDEP-NEXT: entry:355; MDEP-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[ENTRY_IF_END_CRIT_EDGE:%.*]]356; MDEP: entry.if.end_crit_edge:357; MDEP-NEXT: [[RES_PRE:%.*]] = load i32, ptr [[PTR1:%.*]], align 4358; MDEP-NEXT: br label [[IF_END:%.*]]359; MDEP: if.then:360; MDEP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[PTR1]], i32 [[I:%.*]]361; MDEP-NEXT: [[TMP:%.*]] = load i32, ptr [[ARRAYIDX]], align 4362; MDEP-NEXT: store i32 [[TMP]], ptr [[PTR2:%.*]], align 4363; MDEP-NEXT: [[IDX_EXT:%.*]] = sext i32 [[I]] to i64364; MDEP-NEXT: br label [[IF_END]]365; MDEP: if.end:366; MDEP-NEXT: [[RES:%.*]] = phi i32 [ [[RES_PRE]], [[ENTRY_IF_END_CRIT_EDGE]] ], [ [[TMP]], [[IF_THEN]] ]367; MDEP-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY_IF_END_CRIT_EDGE]] ], [ [[IDX_EXT]], [[IF_THEN]] ]368; MDEP-NEXT: [[IDX_TRUNC:%.*]] = trunc i64 [[IDX]] to i32369; MDEP-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[PTR1]], i32 [[IDX_TRUNC]]370; MDEP-NEXT: ret i32 [[RES]]371;372; MSSA-LABEL: @test7(373; MSSA-NEXT: entry:374; MSSA-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]375; MSSA: if.then:376; MSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[PTR1:%.*]], i32 [[I:%.*]]377; MSSA-NEXT: [[TMP:%.*]] = load i32, ptr [[ARRAYIDX]], align 4378; MSSA-NEXT: store i32 [[TMP]], ptr [[PTR2:%.*]], align 4379; MSSA-NEXT: [[IDX_EXT:%.*]] = sext i32 [[I]] to i64380; MSSA-NEXT: br label [[IF_END]]381; MSSA: if.end:382; MSSA-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IDX_EXT]], [[IF_THEN]] ]383; MSSA-NEXT: [[IDX_TRUNC:%.*]] = trunc i64 [[IDX]] to i32384; MSSA-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[PTR1]], i32 [[IDX_TRUNC]]385; MSSA-NEXT: [[RES:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4386; MSSA-NEXT: ret i32 [[RES]]387;388entry:389 br i1 %cond, label %if.then, label %if.end390 391if.then:392 %arrayidx = getelementptr inbounds i32, ptr %ptr1, i32 %i393 %tmp = load i32, ptr %arrayidx, align 4394 store i32 %tmp, ptr %ptr2, align 4395 %idx.ext = sext i32 %i to i64396 br label %if.end397 398if.end:399 %idx = phi i64 [ 0, %entry ], [ %idx.ext, %if.then ]400 %idx.trunc = trunc i64 %idx to i32401 %arrayidx2 = getelementptr inbounds i32, ptr %ptr1, i32 %idx.trunc402 %res = load i32, ptr %arrayidx2, align 4403 ret i32 %res404}405