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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -enable-load-pre -enable-pre -passes=gvn -S < %s | FileCheck %s --check-prefixes=CHECK,MDEP3; RUN: opt -enable-load-pre -enable-pre -passes='gvn<memoryssa>' -S < %s | FileCheck %s --check-prefixes=CHECK,MSSA4 5declare void @side_effect_0() nofree6 7declare void @side_effect_1(i32 %x) nofree8 9declare void @no_side_effect() readonly10 11; TODO: We can PRE the load into the cold path, removing it from the hot path.12define i32 @test_01(ptr %p) {13; CHECK-LABEL: @test_01(14; CHECK-NEXT: entry:15; CHECK-NEXT: br label [[LOOP:%.*]]16; CHECK: loop:17; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]18; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P:%.*]], align 419; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[X]], 10020; CHECK-NEXT: br i1 [[COND]], label [[HOT_PATH:%.*]], label [[COLD_PATH:%.*]]21; CHECK: hot_path:22; CHECK-NEXT: br label [[BACKEDGE]]23; CHECK: cold_path:24; CHECK-NEXT: call void @side_effect_0() #[[ATTR0:[0-9]+]]25; CHECK-NEXT: br label [[BACKEDGE]]26; CHECK: backedge:27; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], [[X]]28; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], 100029; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]30; CHECK: exit:31; CHECK-NEXT: ret i32 [[X]]32;33entry:34 br label %loop35 36loop:37 %iv = phi i32 [ 0, %entry], [%iv.next, %backedge]38 %x = load i32, ptr %p39 %cond = icmp ult i32 %x, 10040 br i1 %cond, label %hot_path, label %cold_path41 42hot_path:43 br label %backedge44 45cold_path:46 call void @side_effect_0() nofree47 br label %backedge48 49backedge:50 %iv.next = add i32 %iv, %x51 %loop.cond = icmp ult i32 %iv.next, 100052 br i1 %loop.cond, label %loop, label %exit53 54exit:55 ret i32 %x56}57 58; TODO: We can PRE the load into the cold path, removing it from the hot path.59define i32 @test_02(ptr %p) {60; CHECK-LABEL: @test_02(61; CHECK-NEXT: entry:62; CHECK-NEXT: br label [[LOOP:%.*]]63; CHECK: loop:64; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]65; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P:%.*]], align 466; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[X]], 10067; CHECK-NEXT: br i1 [[COND]], label [[HOT_PATH:%.*]], label [[COLD_PATH:%.*]]68; CHECK: hot_path:69; CHECK-NEXT: br label [[BACKEDGE]]70; CHECK: cold_path:71; CHECK-NEXT: call void @side_effect_1(i32 [[X]]) #[[ATTR0]]72; CHECK-NEXT: br label [[BACKEDGE]]73; CHECK: backedge:74; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], [[X]]75; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], 100076; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]77; CHECK: exit:78; CHECK-NEXT: ret i32 [[X]]79;80entry:81 br label %loop82 83loop:84 %iv = phi i32 [ 0, %entry], [%iv.next, %backedge]85 %x = load i32, ptr %p86 %cond = icmp ult i32 %x, 10087 br i1 %cond, label %hot_path, label %cold_path88 89hot_path:90 br label %backedge91 92cold_path:93 call void @side_effect_1(i32 %x) nofree94 br label %backedge95 96backedge:97 %iv.next = add i32 %iv, %x98 %loop.cond = icmp ult i32 %iv.next, 100099 br i1 %loop.cond, label %loop, label %exit100 101exit:102 ret i32 %x103}104 105define i32 @test_03(ptr %p) {106; MDEP-LABEL: @test_03(107; MDEP-NEXT: entry:108; MDEP-NEXT: [[X_PRE:%.*]] = load i32, ptr [[P:%.*]], align 4109; MDEP-NEXT: br label [[LOOP:%.*]]110; MDEP: loop:111; MDEP-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]112; MDEP-NEXT: [[COND:%.*]] = icmp ult i32 [[X_PRE]], 100113; MDEP-NEXT: br i1 [[COND]], label [[HOT_PATH:%.*]], label [[COLD_PATH:%.*]]114; MDEP: hot_path:115; MDEP-NEXT: br label [[BACKEDGE]]116; MDEP: cold_path:117; MDEP-NEXT: call void @no_side_effect()118; MDEP-NEXT: br label [[BACKEDGE]]119; MDEP: backedge:120; MDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], [[X_PRE]]121; MDEP-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], 1000122; MDEP-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]123; MDEP: exit:124; MDEP-NEXT: ret i32 [[X_PRE]]125;126; MSSA-LABEL: @test_03(127; MSSA-NEXT: entry:128; MSSA-NEXT: br label [[LOOP:%.*]]129; MSSA: loop:130; MSSA-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]131; MSSA-NEXT: [[X:%.*]] = load i32, ptr [[P:%.*]], align 4132; MSSA-NEXT: [[COND:%.*]] = icmp ult i32 [[X]], 100133; MSSA-NEXT: br i1 [[COND]], label [[HOT_PATH:%.*]], label [[COLD_PATH:%.*]]134; MSSA: hot_path:135; MSSA-NEXT: br label [[BACKEDGE]]136; MSSA: cold_path:137; MSSA-NEXT: call void @no_side_effect()138; MSSA-NEXT: br label [[BACKEDGE]]139; MSSA: backedge:140; MSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], [[X]]141; MSSA-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], 1000142; MSSA-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]143; MSSA: exit:144; MSSA-NEXT: ret i32 [[X]]145;146entry:147 br label %loop148 149loop:150 %iv = phi i32 [ 0, %entry], [%iv.next, %backedge]151 %x = load i32, ptr %p152 %cond = icmp ult i32 %x, 100153 br i1 %cond, label %hot_path, label %cold_path154 155hot_path:156 br label %backedge157 158cold_path:159 call void @no_side_effect()160 br label %backedge161 162backedge:163 %iv.next = add i32 %iv, %x164 %loop.cond = icmp ult i32 %iv.next, 1000165 br i1 %loop.cond, label %loop, label %exit166 167exit:168 ret i32 %x169}170