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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -passes=gvn -S -o - %s | FileCheck %s3 4%struct.sk_buff = type opaque5 6@l2tp_recv_dequeue_session = external dso_local local_unnamed_addr global i32, align 47@l2tp_recv_dequeue_skb = external dso_local local_unnamed_addr global ptr, align 88@l2tp_recv_dequeue_session_2 = external dso_local local_unnamed_addr global i32, align 49@l2tp_recv_dequeue_session_0 = external dso_local local_unnamed_addr global i32, align 410 11declare void @llvm.assume(i1 noundef)12 13define dso_local void @l2tp_recv_dequeue() local_unnamed_addr {14; CHECK-LABEL: define dso_local void @l2tp_recv_dequeue() local_unnamed_addr {15; CHECK-NEXT: [[ENTRY:.*]]:16; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @l2tp_recv_dequeue_session, align 417; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i6418; CHECK-NEXT: [[TMP1:%.*]] = inttoptr i64 [[CONV]] to ptr19; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @l2tp_recv_dequeue_session_2, align 420; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP2]], 021; CHECK-NEXT: br label %[[FOR_COND:.*]]22; CHECK: [[FOR_COND]]:23; CHECK-NEXT: [[STOREMERGE:%.*]] = phi ptr [ [[TMP1]], %[[ENTRY]] ], [ null, %[[IF_END:.*]] ]24; CHECK-NEXT: store ptr [[STOREMERGE]], ptr @l2tp_recv_dequeue_skb, align 825; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label %[[IF_END]], label %[[IF_THEN:.*]]26; CHECK: [[IF_THEN]]:27; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[STOREMERGE]], align 428; CHECK-NEXT: store i32 [[TMP3]], ptr @l2tp_recv_dequeue_session_0, align 429; CHECK-NEXT: callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"()30; CHECK-NEXT: to label %[[ASM_FALLTHROUGH_I:.*]] [label %if.end]31; CHECK: [[ASM_FALLTHROUGH_I]]:32; CHECK-NEXT: br label %[[IF_END]]33; CHECK: [[IF_END]]:34; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[STOREMERGE]], align 435; CHECK-NEXT: [[TOBOOL2_NOT:%.*]] = icmp eq i32 [[TMP4]], 036; CHECK-NEXT: tail call void @llvm.assume(i1 [[TOBOOL2_NOT]])37; CHECK-NEXT: br label %[[FOR_COND]]38;39entry:40 %0 = load i32, ptr @l2tp_recv_dequeue_session, align 441 %conv = sext i32 %0 to i6442 %1 = inttoptr i64 %conv to ptr43 %2 = load i32, ptr @l2tp_recv_dequeue_session_2, align 444 %tobool.not = icmp eq i32 %2, 045 br label %for.cond46 47for.cond: ; preds = %if.end, %entry48 %storemerge = phi ptr [ %1, %entry ], [ null, %if.end ]49 store ptr %storemerge, ptr @l2tp_recv_dequeue_skb, align 850 br i1 %tobool.not, label %if.end, label %if.then51 52if.then: ; preds = %for.cond53 %3 = load i32, ptr %storemerge, align 454 store i32 %3, ptr @l2tp_recv_dequeue_session_0, align 455; Splitting the critical edge from if.then to if.end will fail, but should not56; cause an infinite loop in GVN. If we can one day split edges of callbr57; indirect targets, great!58 callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"()59 to label %asm.fallthrough.i [label %if.end]60 61asm.fallthrough.i: ; preds = %if.then62 br label %if.end63 64if.end: ; preds = %asm.fallthrough.i, %if.then, %for.cond65 %4 = load i32, ptr %storemerge, align 466 %tobool2.not = icmp eq i32 %4, 067 tail call void @llvm.assume(i1 %tobool2.not)68 br label %for.cond69}70